From f91538c3eca7529810922ee6f39ff2ea767162fa Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 7 Feb 2022 08:00:59 +0100 Subject: sb/intel/ibexpeak/azalia.c: Use 'pci_{and,or}_config' Change-Id: Iafe1a3476c0afa5ebfb75fb704429594e24e96f2 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/61662 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/ibexpeak/azalia.c | 42 +++++++++------------------------ 1 file changed, 11 insertions(+), 31 deletions(-) (limited to 'src') diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 17db658333..d4e639ac04 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -40,8 +40,6 @@ static void azalia_init(struct device *dev) u8 *base; struct resource *res; u32 codec_mask; - u8 reg8; - u16 reg16; u32 reg32; /* Find base address */ @@ -61,33 +59,21 @@ static void azalia_init(struct device *dev) reg32 |= RCBA32(0x2030) & 0xfe; pci_write_config32(dev, 0x120, reg32); - reg16 = pci_read_config16(dev, 0x78); - reg16 |= (1 << 11); - pci_write_config16(dev, 0x78, reg16); + pci_or_config16(dev, 0x78, 1 << 11); } else printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); - reg32 = pci_read_config32(dev, 0x114); - reg32 &= ~0xfe; - pci_write_config32(dev, 0x114, reg32); + pci_and_config32(dev, 0x114, ~0xfe); // Set VCi enable bit - reg32 = pci_read_config32(dev, 0x120); - reg32 |= (1 << 31); - pci_write_config32(dev, 0x120, reg32); + pci_or_config32(dev, 0x120, 1 << 31); // Enable HDMI codec: - reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 1); - pci_write_config32(dev, 0xc4, reg32); + pci_or_config32(dev, 0xc4, 1 << 1); - reg8 = pci_read_config8(dev, 0x43); - reg8 |= (1 << 6); - pci_write_config8(dev, 0x43, reg8); + pci_or_config8(dev, 0x43, 1 << 6); - reg32 = pci_read_config32(dev, 0xd0); - reg32 &= ~(1 << 31); - pci_write_config32(dev, 0xd0, reg32); + pci_and_config32(dev, 0xd0, ~(1 << 31)); /* Set Bus Master */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -103,14 +89,11 @@ static void azalia_init(struct device *dev) /* Wait 1ms */ udelay(1000); - // - reg8 = pci_read_config8(dev, 0x40); // Audio Control - reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb - pci_write_config8(dev, 0x40, reg8); + // Select Azalia mode. This needs to be controlled via devicetree.cb + pci_or_config8(dev, 0x40, 1); // Audio Control - reg8 = pci_read_config8(dev, 0x4d); // Docking Status - reg8 &= ~(1 << 7); // Docking not supported - pci_write_config8(dev, 0x4d, reg8); + // Docking not supported + pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status codec_mask = codec_detect(base); @@ -120,10 +103,7 @@ static void azalia_init(struct device *dev) } /* Enable dynamic clock gating */ - reg8 = pci_read_config8(dev, 0x43); - reg8 &= ~0x7; - reg8 |= (1 << 2) | (1 << 0); - pci_write_config8(dev, 0x43, reg8); + pci_update_config8(dev, 0x43, ~0x07, (1 << 2) | (1 << 0)); } static struct device_operations azalia_ops = { -- cgit v1.2.3