From f81c589ad25580b82a0c61031168385e8057293d Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 24 Apr 2019 10:19:07 -0600 Subject: soc/intel/apollolake/bootblock: Clear the GPI IS & IE registers Clear the GPI Interrupt Status & Enable registers to prevent any interrupt storms due to GPI. BUG=b:130593883 BRANCH=octopus TEST=Ensure that the Interrupt status & enable registers are reset during the boot up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: Ia3b9d3bf08472219348e20b53bae470c589039fb Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/32448 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/bootblock/bootblock.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src') diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index ac6903a9d2..c791378f13 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -122,3 +122,12 @@ void bootblock_soc_early_init(void) paging_enable_for_car("pdpt", "pt"); } } + +void bootblock_soc_init(void) +{ + /* + * Clear the GPI interrupt enable & status registers to avoid any + * interrupt storm during the kernel bootup. + */ + gpi_clear_int_cfg(); +} -- cgit v1.2.3