From f733703a61d291ec300a233bed03c27d53ae6b1f Mon Sep 17 00:00:00 2001 From: Kun Liu Date: Thu, 30 Nov 2023 18:05:03 +0800 Subject: mb/google/rex/var/screebo: Add delay 1ms after Main 3V3 when S0ix returns S0, PERST needs to delay until Main 3V3 is stable and then pull up BUG=b:313976507 TEST=emerge-rex coreboot,measurement waveform verify pass Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0 Signed-off-by: Kun Liu Reviewed-on: https://review.coreboot.org/c/coreboot/+/79320 Reviewed-by: Rui Zhou Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/google/rex/variants/screebo/overridetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index f6b32dbdde..86bd74d0b1 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -289,6 +289,7 @@ chip soc/intel/meteorlake chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)" + register "enable_delay_ms" = "1" register "srcclk_pin" = "6" device generic 0 on probe DB_SD SD_GL9750 -- cgit v1.2.3