From f6d3bd4815d2d442eb3cdf418ba3074134e5bd7d Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Thu, 6 Aug 2015 19:22:53 +0100 Subject: imgtec/pistachio: increase CBFS cache Increase CBFS cache size to allow for a bigger payload. Change-Id: I47404ba9bbe95f6610189b971504019c0a1a81f0 Signed-off-by: Ionela Voinescu Reviewed-on: https://review.coreboot.org/12762 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index ce0063f38c..edf9c41493 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -26,8 +26,8 @@ SECTIONS DRAM_START(0x00000000) /* DMA coherent area: accessed via KSEG1. */ DMA_COHERENT(0x00100000, 1M) - POSTRAM_CBFS_CACHE(0x00200000, 192K) - RAMSTAGE(0x00230000, 128K) + POSTRAM_CBFS_CACHE(0x00200000, 512K) + RAMSTAGE(0x00280000, 128K) /* * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock -- cgit v1.2.3