From f69cb29c20e40750e7b0595852ea9030050ebe2a Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 29 Sep 2022 16:05:41 +0200 Subject: soc/amd/picasso/fch: use [read,write]8p to avoid typecasts Signed-off-by: Felix Held Change-Id: I8445f209e43366b43b9c4750bc5f074f6d4144aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/67978 Reviewed-by: Raul Rangel Reviewed-by: Fred Reitberger Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas --- src/soc/amd/picasso/fch.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index c4d34a5301..b83e700e57 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -165,12 +165,12 @@ static void al2ahb_clock_gate(void) uint8_t al2ahb_val; uintptr_t al2ahb_base = ALINK_AHB_ADDRESS; - al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET)); + al2ahb_val = read8p(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET); al2ahb_val |= AL2AHB_CLK_GATE_EN; - write8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET), al2ahb_val); - al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET)); + write8p(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET, al2ahb_val); + al2ahb_val = read8p(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET); al2ahb_val |= AL2AHB_HCLK_GATE_EN; - write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val); + write8p(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET, al2ahb_val); } /* configure the general purpose PCIe clock outputs according to the devicetree settings */ -- cgit v1.2.3