From f5b9e9aed11b3c4909aba8159c2b66e7ecd67a66 Mon Sep 17 00:00:00 2001 From: zengqinghong Date: Wed, 21 Aug 2024 13:57:06 +0800 Subject: mb/google/nissa/var/teliks: Adjust usb2 pin of wlan Since the voltage value measured by the USB2 pin of the wlan is 500mv, it does not meet the design requirements. Adjusting the port length can reduce the voltage to 450mv, which meets the expected settings. BUG=b:361037189 TEST=1. The voltage measurements are as expected. 2. The Bluetooth and WiFi functions of the wlan module are verified to be normal. Change-Id: Icd1ec3b561ee5b3f55e5f97a56fd9cb7df893508 Signed-off-by: zengqinghong Reviewed-on: https://review.coreboot.org/c/coreboot/+/84001 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Weimin Wu --- src/mainboard/google/brya/variants/teliks/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/brya/variants/teliks/overridetree.cb b/src/mainboard/google/brya/variants/teliks/overridetree.cb index 6ca555abec..2f4534f0df 100644 --- a/src/mainboard/google/brya/variants/teliks/overridetree.cb +++ b/src/mainboard/google/brya/variants/teliks/overridetree.cb @@ -460,8 +460,8 @@ chip soc/intel/alderlake register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch) register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch) register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch) - register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch) - register "usb2_ports[9]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth port for CNVi WLAN + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch) + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB)) register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB) -- cgit v1.2.3