From f5b3a49b76e3feeb617c51df432d36bdb043a0ce Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Tue, 11 Aug 2020 18:28:29 +0530 Subject: mb/intel/jslrvp: Correct PCI root port mapping Jasper Lake SoC had PCI root port mapping swap, thats why we were using swapped mapping earlier for all the boards Recently, patch was pushed to handle this swap in PCI enumeration code for Jasper Lake and we need to correct this mapping. Now this mapping aligns with actual port mapping in the schematics BUG=None BRANCH=None TEST=NVMe and WLAN are getting detected after this changes Change-Id: Ide5f8419a15f559cefeb6039f155fabf97c279f8 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/44391 Tested-by: build bot (Jenkins) Reviewed-by: Ronak Kanabar Reviewed-by: Sugnan Prabhu S Reviewed-by: Subrata Banik --- src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index c5a3fc30bc..268d239c06 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -416,12 +416,12 @@ chip soc/intel/jasperlake device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 - WLAN device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.4 on end # PCI Express Port 5 - NVMe + device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 device pci 1e.0 on end # UART #0 -- cgit v1.2.3