From f3a8bf13cbfc43e45f0bb6e451608a082b59f7bf Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 2 Mar 2021 09:31:15 -0800 Subject: soc/intel/alderlake: Drop 100ms delay and do not poll Link Active Drop the 100ms delay in the _PS0 method because kernel already adds this 100ms. This change also drops polling TBT PCIe root ports Link Active State because this scheme is not applicable for SW CM. BUG=None TEST=Built Alderlake coreboot image successfully. Signed-off-by: John Zhao Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/acpi/tcss_pcierp.asl | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'src') diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl index 3f495be680..07d024a027 100644 --- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -140,18 +140,6 @@ Method (D3CX, 0, Serialized) Local1 = L23R } STAT = 0x1 - - /* Wait for LA = 1 */ - Local0 = 0 - Local1 = LASX - While (Local1 == 0) { - If (Local0 > 20) { - Break - } - Sleep(5) - Local0++ - Local1 = LASX - } } /* @@ -192,8 +180,6 @@ Method (_PS0, 0, Serialized) If (PMEX == 1) { PMEX = 0 /* Disable Power Management SCI */ } - - Sleep(100) /* Wait for 100ms before return to OS starts any OS activities. */ } Method (_PS3, 0, Serialized) -- cgit v1.2.3