From f349672966fcde4f943c2a5de3c086971aaded44 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 21 Aug 2018 10:50:16 -0700 Subject: mb/intel/coffelake_rvp: Implement mainboard memory information Turn on SOC_INTEL_CANNONLAKE_MEMCFG_INT for coffeelake rvp platform for easier collabration on newer platform. The setting in memory.c get from board design itself. BUG=N/A TEST=Build and boot up with whiskey lake rvp platform. Change-Id: I10f3af4bed511153cef4d6f3a93caea57cc4ae90 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/28257 Reviewed-by: Pratikkumar V Prajapati Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/mainboard/intel/coffeelake_rvp/Kconfig | 1 + src/mainboard/intel/coffeelake_rvp/Makefile.inc | 3 +- src/mainboard/intel/coffeelake_rvp/memory.c | 55 +++++++++++++++++ src/mainboard/intel/coffeelake_rvp/romstage.c | 39 ++++-------- .../intel/coffeelake_rvp/spd/Makefile.inc | 28 --------- .../intel/coffeelake_rvp/spd/empty.spd.hex | 32 ---------- .../coffeelake_rvp/spd/samsung_ddr4_4GB.spd.hex | 32 ---------- .../coffeelake_rvp/spd/samsung_lpddr4_8GB.spd.hex | 32 ---------- src/mainboard/intel/coffeelake_rvp/spd/spd.h | 28 --------- src/mainboard/intel/coffeelake_rvp/spd/spd_util.c | 71 ---------------------- .../baseboard/include/baseboard/variants.h | 4 ++ 11 files changed, 73 insertions(+), 252 deletions(-) create mode 100644 src/mainboard/intel/coffeelake_rvp/memory.c delete mode 100644 src/mainboard/intel/coffeelake_rvp/spd/Makefile.inc delete mode 100644 src/mainboard/intel/coffeelake_rvp/spd/empty.spd.hex delete mode 100644 src/mainboard/intel/coffeelake_rvp/spd/samsung_ddr4_4GB.spd.hex delete mode 100644 src/mainboard/intel/coffeelake_rvp/spd/samsung_lpddr4_8GB.spd.hex delete mode 100644 src/mainboard/intel/coffeelake_rvp/spd/spd.h delete mode 100644 src/mainboard/intel/coffeelake_rvp/spd/spd_util.c (limited to 'src') diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index fe0e9dbe01..49fba665ea 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select SOC_INTEL_COFFEELAKE + select SOC_INTEL_CANNONLAKE_MEMCFG_INIT config MAINBOARD_DIR string diff --git a/src/mainboard/intel/coffeelake_rvp/Makefile.inc b/src/mainboard/intel/coffeelake_rvp/Makefile.inc index 7bf3edb6cc..274645370a 100644 --- a/src/mainboard/intel/coffeelake_rvp/Makefile.inc +++ b/src/mainboard/intel/coffeelake_rvp/Makefile.inc @@ -14,14 +14,13 @@ ## GNU General Public License for more details. ## -subdirs-y += spd - bootblock-y += bootblock.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += memory.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/coffeelake_rvp/memory.c b/src/mainboard/intel/coffeelake_rvp/memory.c new file mode 100644 index 0000000000..7058be4130 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/memory.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +static const struct cnl_mb_cfg baseboard_memcfg_cfg = { + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = { 0, 1, 3, 2, 4, 5, 6, 7 }, + .dqs_map[DDR_CH1] = { 1, 0, 4, 5, 2, 3, 6, 7 }, + + /* Baseboard uses 121, 81 and 100 rcomp resistors */ + .rcomp_resistor = { 121, 81, 100 }, + + /* + * Baseboard Rcomp target values. + */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* Baseboard is an interleaved design */ + .dq_pins_interleaved = 1, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Disable Early Command Training */ + .ect = 0, +}; + +const struct cnl_mb_cfg *__weak variant_memcfg_config(void) +{ + return &baseboard_memcfg_cfg; +} diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c index 475a8155fe..1ea353725a 100644 --- a/src/mainboard/intel/coffeelake_rvp/romstage.c +++ b/src/mainboard/intel/coffeelake_rvp/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Google Inc. - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2017-20188 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,34 +14,19 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include +#include +#include #include -#include "spd/spd.h" -#include -#include -void mainboard_memory_init_params(FSPM_UPD *mupd) +void mainboard_memory_init_params(FSPM_UPD *memupd) { - FSP_M_CONFIG *mem_cfg; - mem_cfg = &mupd->FspmConfig; + const struct spd_info spd = { + .spd_smbus_address[0] = 0xA0, + .spd_smbus_address[1] = 0xA2, + .spd_smbus_address[2] = 0xA4, + .spd_smbus_address[3] = 0xA6, + }; - mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); - mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0); - mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - - mem_cfg->DqPinsInterleaved = 1; - mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA/CHB */ - mem_cfg->ECT = 1; /* Early Command Training Enabled */ - - /* Setting standard SPD addresses */ - mem_cfg->SpdAddressTable[0] = 0xA0; - mem_cfg->SpdAddressTable[1] = 0xA2; - mem_cfg->SpdAddressTable[2] = 0xA4; - mem_cfg->SpdAddressTable[3] = 0xA6; + cannonlake_memcfg_init(&memupd->FspmConfig, + variant_memcfg_config(), &spd); } diff --git a/src/mainboard/intel/coffeelake_rvp/spd/Makefile.inc b/src/mainboard/intel/coffeelake_rvp/spd/Makefile.inc deleted file mode 100644 index f7288566a4..0000000000 --- a/src/mainboard/intel/coffeelake_rvp/spd/Makefile.inc +++ /dev/null @@ -1,28 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2018 Intel Corporation. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += spd_util.c - -SPD_BIN = $(obj)/spd.bin - -SPD_SOURCES = empty # 0b000 -SPD_SOURCES += samsung_ddr4_4GB # 0b001 Dual Channel 4GB -SPD_SOURCES += samsung_lpddr4_8GB # 0b001 Dual Channel 8GB -SPD_SOURCES += empty # 0b011 -SPD_SOURCES += empty # 0b100 -SPD_SOURCES += empty # 0b101 -SPD_SOURCES += empty # 0b110 -SPD_SOURCES += empty # 0b111 diff --git a/src/mainboard/intel/coffeelake_rvp/spd/empty.spd.hex b/src/mainboard/intel/coffeelake_rvp/spd/empty.spd.hex deleted file mode 100644 index 67b46cd239..0000000000 --- a/src/mainboard/intel/coffeelake_rvp/spd/empty.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 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00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/coffeelake_rvp/spd/samsung_ddr4_4GB.spd.hex b/src/mainboard/intel/coffeelake_rvp/spd/samsung_ddr4_4GB.spd.hex deleted file mode 100644 index 49db2374f4..0000000000 --- a/src/mainboard/intel/coffeelake_rvp/spd/samsung_ddr4_4GB.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 11 0C 03 84 19 00 08 00 60 00 03 01 03 00 00 -00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E 20 08 -00 05 70 03 00 A8 18 28 28 00 78 00 14 3C 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 -16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 64 20 -0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 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00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/coffeelake_rvp/spd/samsung_lpddr4_8GB.spd.hex b/src/mainboard/intel/coffeelake_rvp/spd/samsung_lpddr4_8GB.spd.hex deleted file mode 100644 index d298629342..0000000000 --- a/src/mainboard/intel/coffeelake_rvp/spd/samsung_lpddr4_8GB.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -23 10 10 0E 15 19 95 08 00 40 00 00 0A 22 00 00 -48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0 -02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 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a/src/mainboard/intel/coffeelake_rvp/spd/spd.h b/src/mainboard/intel/coffeelake_rvp/spd/spd.h deleted file mode 100644 index 036b5be888..0000000000 --- a/src/mainboard/intel/coffeelake_rvp/spd/spd.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define RCOMP_TARGET_PARAMS 0x5 - -void mainboard_fill_dq_map_ch0(void *dq_map_ptr); -void mainboard_fill_dq_map_ch1(void *dq_map_ptr); -void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); -void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); -void mainboard_fill_rcomp_res_data(void *rcomp_ptr); -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); -#endif diff --git a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c deleted file mode 100644 index 73f354d741..0000000000 --- a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include -#include -#include "spd.h" - -void mainboard_fill_dq_map_ch0(void *dq_map_ptr) -{ - /* DQ byte map Ch0 */ - const u8 dq_map[12] = { - 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dq_map_ch1(void *dq_map_ptr) -{ - const u8 dq_map[12] = { - 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; - - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_h[8] = { 0, 1, 3, 2, 4, 5, 6, 7 }; - - memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h)); -} - -void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_h[8] = { 1, 0, 4, 5, 2, 3, 6, 7 }; - - memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h)); -} - -void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 100, 100, 100 }; - memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); -} - -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { - 100, 33, 32, 33, 28 }; - - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h index cdae0f9738..64ff69fcd4 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -16,6 +16,7 @@ #ifndef __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__ +#include #include #include #include @@ -28,6 +29,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); +/* Return memory configuration structure. */ +const struct cnl_mb_cfg *variant_memcfg_config(void); + /* Seed the NHLT tables with the board specific information. */ struct nhlt; void variant_nhlt_init(struct nhlt *nhlt); -- cgit v1.2.3