From f2a50d1231e7c736b526c0583c4fb4186216b3ff Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Wed, 18 May 2016 13:45:20 -0700 Subject: soc/intel/common: Add _OSC method Not masking any bits in Operating System Capabilities, which means we support all the capabilities that OS passed in Arg3 Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5 Signed-off-by: Hannah Williams Reviewed-on: https://review.coreboot.org/15021 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/common/acpi/pci_osc.asl | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 src/soc/intel/common/acpi/pci_osc.asl (limited to 'src') diff --git a/src/soc/intel/common/acpi/pci_osc.asl b/src/soc/intel/common/acpi/pci_osc.asl new file mode 100644 index 0000000000..4179e94ae7 --- /dev/null +++ b/src/soc/intel/common/acpi/pci_osc.asl @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define PCI_OSC_UUID "33DB4D5B-1FF7-401C-9657-7441C03DD766" + +Scope (\_SB.PCI0) { + Method (_OSC, 4) { + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID (PCI_OSC_UUID))) { + /* Let OS control everything */ + Return (Arg3) + } Else { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } +} -- cgit v1.2.3