From f1a3f187ba253d133a85a6c9ad29e426d8b25f55 Mon Sep 17 00:00:00 2001 From: Won Chung Date: Tue, 25 Jan 2022 22:30:12 +0000 Subject: mb/google/brya: Add custom PLD fields to devicetree for brya reference For USB ports, we want to use custom PLD fields with more details to indicate physical location. Custom PLD will also be added to other brya variants in the future as we figure out physical port locations on those devices. Type A port on MLB is removed since it is no longer used. BUG=b:216490477 TEST=emerge-brya coreboot & SSDT dump in Brya test device Signed-off-by: Won Chung Change-Id: Iea975a4f436a204d4edd19fad0f5652fb44c6301 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61388 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai Reviewed-by: Tim Wawrzynczak Reviewed-by: Nick Vaccaro --- .../google/brya/variants/brya0/overridetree.cb | 76 ++++++++++++++++------ .../google/brya/variants/brya4es/overridetree.cb | 76 ++++++++++++++++------ 2 files changed, 112 insertions(+), 40 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index c97ff33657..e7e7f73e8c 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -663,19 +663,37 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_CENTER, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(1, 1)}" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(2, 1)}" device ref tcss_usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(3, 1)}" device ref tcss_usb3_port3 on end end end @@ -687,19 +705,37 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_CENTER, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(1, 1)}" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(2, 1)}" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(3, 1)}" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -714,16 +750,16 @@ chip soc/intel/alderlake probe UFC UFC_USB end end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port (MLB)"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" - device ref usb2_port8 on end - end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, + .group = ACPI_PLD_GROUP(1, 2)}" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -736,15 +772,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, + .group = ACPI_PLD_GROUP(1, 2)}" device ref usb3_port1 on end end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port (MLB)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" - device ref usb3_port2 on end - end chip drivers/usb/acpi register "desc" = ""USB3 WWAN"" register "type" = "UPC_TYPE_INTERNAL" diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb index 59cd8c4b40..dd5650e5a8 100644 --- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb @@ -659,19 +659,37 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_CENTER, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(1, 1)}" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(2, 1)}" device ref tcss_usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(3, 1)}" device ref tcss_usb3_port3 on end end end @@ -683,19 +701,37 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_CENTER, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(1, 1)}" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(2, 1)}" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_LEFT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_OVAL, + .group = ACPI_PLD_GROUP(3, 1)}" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -710,16 +746,16 @@ chip soc/intel/alderlake probe UFC UFC_USB end end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port (MLB)"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" - device ref usb2_port8 on end - end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, + .group = ACPI_PLD_GROUP(1, 2)}" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -732,15 +768,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "use_custom_pld" = "true" + register "custom_pld" = "{ + .visible = true, + .panel = PLD_PANEL_RIGHT, + .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, + .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, + .group = ACPI_PLD_GROUP(1, 2)}" device ref usb3_port1 on end end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port (MLB)"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" - device ref usb3_port2 on end - end chip drivers/usb/acpi register "desc" = ""USB3 WWAN"" register "type" = "UPC_TYPE_INTERNAL" -- cgit v1.2.3