From f16d904192dc9173c526ae20eb26c910caf21fa2 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 18 Feb 2016 16:06:21 -0800 Subject: RISC-V: Make inline asm usage safer Change-Id: Id547c98e876e9fd64fa4d12239a2608bfd2495d2 Signed-off-by: Andrew Waterman Reviewed-on: https://review.coreboot.org/13735 Reviewed-by: Ronald G. Minnich Tested-by: build bot (Jenkins) --- src/arch/riscv/trap_handler.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 16b66d8314..53bcbf98c1 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -84,20 +84,18 @@ void handle_supervisor_call(trapframe *tf) { void trap_handler(trapframe *tf) { write_csr(mscratch, tf); - int cause = 0; - void* epc = 0; - void* badAddr = 0; + uintptr_t cause; + void *epc; + void *badAddr; // extract cause - asm("csrr t0, mcause"); - asm("move %0, t0" : "=r"(cause)); + asm("csrr %0, mcause" : "=r"(cause)); // extract faulting Instruction pc epc = (void*) tf->epc; // extract bad address - asm("csrr t0, mbadaddr"); - asm("move %0, t0" : "=r"(badAddr)); + asm("csrr %0, mbadaddr" : "=r"(badAddr)); switch(cause) { case 0: -- cgit v1.2.3