From f0ed846cfce843965f191e56ba01b35d8c9195b0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 2 May 2022 16:52:57 +0200 Subject: arch/x86/acpi: Consolidate POST code handling Move ASL POST code declarations into a common file to avoid redundancy. Also, provide a dummy implementation when `POST_IO` is not enabled, as the value of `CONFIG_POST_IO_PORT` can't be used. Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/63988 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Lean Sheng Tan --- src/arch/x86/acpi/post.asl | 17 +++++++++++++++++ src/mainboard/asus/p2b/dsdt.asl | 8 +------- src/mainboard/intel/cedarisland_crb/acpi/platform.asl | 8 +------- src/soc/intel/common/acpi/platform.asl | 8 +------- src/southbridge/intel/common/acpi/platform.asl | 8 +------- 5 files changed, 21 insertions(+), 28 deletions(-) create mode 100644 src/arch/x86/acpi/post.asl (limited to 'src') diff --git a/src/arch/x86/acpi/post.asl b/src/arch/x86/acpi/post.asl new file mode 100644 index 0000000000..dbdc68110f --- /dev/null +++ b/src/arch/x86/acpi/post.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#if CONFIG(POST_IO) + +/* POST code support, typically on port 80 */ +OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +#else + +/* Dummy placeholder to avoid issues */ +Name (DBG0, 0) + +#endif diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 25515d22e9..5d53c1dfa6 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -22,13 +22,7 @@ DefinitionBlock ( #include /* \_SB scope defining the main processor is generated in SSDT. */ - /* Port 80 POST */ - - OperationRegion (POST, SystemIO, 0x80, 1) - Field (POST, ByteAcc, Lock, Preserve) - { - DBG0, 8 - } + #include /* * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 diff --git a/src/mainboard/intel/cedarisland_crb/acpi/platform.asl b/src/mainboard/intel/cedarisland_crb/acpi/platform.asl index 3bebbff940..5f7ffbb94d 100644 --- a/src/mainboard/intel/cedarisland_crb/acpi/platform.asl +++ b/src/mainboard/intel/cedarisland_crb/acpi/platform.asl @@ -9,13 +9,7 @@ Field (APMP, ByteAcc, NoLock, Preserve) APMS, 8 // APM status } -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} +#include Name(\APC1, Zero) // IIO IOAPIC diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 3bb2f53046..c988e0a43f 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -7,13 +7,7 @@ External(\_SB.MWAK, MethodObj) External(\_SB.PCI0.EGPM, MethodObj) External(\_SB.PCI0.RGPM, MethodObj) -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} +#include /* * The _PTS method (Prepare To Sleep) is called before the OS is diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index ec7d680ded..e044f04822 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -9,13 +9,7 @@ Field (APMP, ByteAcc, NoLock, Preserve) APMS, 8 // APM status } -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} +#include #if CONFIG(ACPI_SOC_NVS) /* SMI I/O Trap */ -- cgit v1.2.3