From f077de66ffdbbd191f09ae8a4d6f08d0313be90f Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Mon, 6 Jul 2015 16:42:56 +0530 Subject: Sklrvp: Select PCIEXP_L1_SUB_STATE config symbol This patch selects the config symbol PCIEXP_L1_SUB_STATE to enable L1 substate for PCIe. BRANCH=None BUG=chrome-os-partner:42331 TEST=Build for sklrvp; boot and check "dmesg | grep iwl" shows "L1 enabled and LTR enabled" Change-Id: I97552c7700649a9f5d8646a03027c5c5e0b477b4 Signed-off-by: Patrick Georgi Original-Commit-Id: d3115816fbdd11c7f8ff418e0b5c86b8650c8b83 Original-Change-Id: Iaf307cb2d623cc1ce97b01d15a6b42569fd0c0c4 Original-Signed-off-by: Naveen Krishna Chatradhi Original-Reviewed-on: https://chromium-review.googlesource.com/284775 Original-Reviewed-by: Aaron Durbin Original-Tested-by: Wenkai Du Reviewed-on: http://review.coreboot.org/10988 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Paul Menzel --- src/mainboard/intel/sklrvp/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mainboard/intel/sklrvp/Kconfig b/src/mainboard/intel/sklrvp/Kconfig index 4c764c0804..22ce4735ec 100644 --- a/src/mainboard/intel/sklrvp/Kconfig +++ b/src/mainboard/intel/sklrvp/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MARK_GRAPHICS_MEM_WRCOMB select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR + select PCIEXP_L1_SUB_STATE select INTEL_PCH_UART_CONSOLE select SOC_INTEL_SKYLAKE select VBOOT_DYNAMIC_WORK_BUFFER -- cgit v1.2.3