From f0277dbbe665e7af21868358b92bdfad617dcba2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 20 Feb 2024 19:12:25 +0530 Subject: mb/google/rex/var/screebo: Refactor SSD power sequencing Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) | v ramstage (A19/1, A20/1) Ideally, we don't need SSD power sequencing at ramstage, but due to the fact that Screebo has RO locked, any change in the bootblock won't be applicable for FSI'ed screebo devices. Therefore, we're keeping the existing ramstage power sequencing flow as is. TEST=Able to build and boot google/screebo using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: I0ee1fa4613178da8771c9e6b5ee871e50ea6324c Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/80640 Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- src/mainboard/google/rex/variants/screebo/gpio.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/rex/variants/screebo/gpio.c b/src/mainboard/google/rex/variants/screebo/gpio.c index 91a9ba0385..9149fb44d0 100644 --- a/src/mainboard/google/rex/variants/screebo/gpio.c +++ b/src/mainboard/google/rex/variants/screebo/gpio.c @@ -376,6 +376,9 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ @@ -399,6 +402,9 @@ static const struct pad_config early_gpio_table[] = { /* GPP_H10 : [] ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), + + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), }; static const struct pad_config romstage_gpio_table[] = { @@ -410,6 +416,8 @@ static const struct pad_config romstage_gpio_table[] = { PAD_CFG_GPO(GPP_C21, 0, DEEP), /* GPP_D02 : [] ==> SD_PERST_L */ PAD_CFG_GPO(GPP_D02, 1, DEEP), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 1, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) -- cgit v1.2.3