From ec5a947b44f1f2bd2bd90071df2617de608cd1c2 Mon Sep 17 00:00:00 2001 From: marxwang Date: Mon, 11 Dec 2017 14:57:49 +0800 Subject: soc/intel/skylake: make tcc_offset take effect Currently, "tcc_offset" defined in devicetree is overwritten by Intel FSP-S UPD "TccActivationOffset". This patch will make "TccActivationOffset" refer to "tcc_offset". TEST=check if MSR (0x1a2[29:24]) value is updated with "tcc_offset" by iotools (rdmsr 0 0x1a2). Change-Id: Ibc6f33bea19a1d59bc7e407815210942b38f0702 Signed-off-by: marxwang Reviewed-on: https://review.coreboot.org/22818 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel --- src/soc/intel/skylake/chip_fsp20.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index f4060b2d99..2df013f563 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -290,6 +290,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable/Disable EIST */ tconfig->Eist = config->eist_enable; + /* Set TccActivationOffset */ + tconfig->TccActivationOffset = config->tcc_offset; + soc_irq_settings(params); } -- cgit v1.2.3