From ec0a85b5807320695a89cba6bffcaca6d0bbc0f1 Mon Sep 17 00:00:00 2001 From: Harsha B R Date: Fri, 16 Dec 2022 12:30:28 +0530 Subject: mb/intel/mtlrvp: Configure GPIO Tier-1 GPEs for MTL-RVP Configure GPIO Tier-1 GPE's that defines the route for GPE events for MTL-RVP. Configure GPE route as below, PMC_GPE0_DW0 -> GPP_B PMC_GPE0_DW1 -> GPP_D PMC_GPE0_DW2 -> GPP_E BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to ChromeOS using subsequent patches in the train Signed-off-by: Harsha B R Change-Id: Ieab95b72ade75734b0788a32566649d90acbc48a Signed-off-by: Jamie Ryu Reviewed-on: https://review.coreboot.org/c/coreboot/+/70872 Reviewed-by: Eric Lai Reviewed-by: Krishna P Bhat D Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src') diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 649a44f8fd..10b4cea335 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -1,5 +1,10 @@ chip soc/intel/meteorlake + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" -- cgit v1.2.3