From eb789f0b79aa99e214ccefc04f9f78b550f52f32 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 27 Oct 2018 16:40:25 +0200 Subject: src: Use include when appropriate Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/arch/x86/cf9_reset.c | 1 - src/cpu/amd/family_10h-family_15h/init_cpus.h | 1 - src/cpu/intel/fsp_model_406dx/bootblock.c | 1 - src/drivers/intel/fsp2_0/stage_cache.c | 1 - src/ec/google/chromeec/ec.c | 1 - src/lib/hardwaremain.c | 1 - src/mainboard/google/foster/pmic.c | 2 +- src/mainboard/google/smaug/pmic.c | 2 +- src/mainboard/google/veyron/bootblock.c | 1 - src/mainboard/google/veyron_mickey/bootblock.c | 1 - src/mainboard/google/veyron_rialto/bootblock.c | 1 - src/security/tpm/tspi/tspi.c | 1 - src/security/vboot/common.c | 1 - src/soc/cavium/common/bdk-coreboot.c | 1 - src/soc/intel/braswell/romstage/romstage.c | 1 - src/soc/intel/common/block/cpu/cpulib.c | 1 - src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 1 - src/soc/intel/skylake/romstage/romstage.c | 1 - src/southbridge/amd/agesa/hudson/early_setup.c | 2 +- src/southbridge/amd/pi/hudson/early_setup.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 1 - src/southbridge/nvidia/ck804/early_setup_car.c | 2 ++ 22 files changed, 6 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c index c28e4488a6..d1e5704ceb 100644 --- a/src/arch/x86/cf9_reset.c +++ b/src/arch/x86/cf9_reset.c @@ -18,7 +18,6 @@ #include #include #include -#include /* * A system reset in terms of the CF9 register asserts the INIT# diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h index 65649d6845..d09fc8241c 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.h +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -22,7 +22,6 @@ #include #include #include -#include #include #include "defaults.h" diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 2ffbd8b09c..14cfad9de1 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include "model_406dx.h" diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c index 434eae944a..a9ec154d38 100644 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -17,7 +17,6 @@ #include #include #include -#include #include void stage_cache_external_region(void **base, size_t *size) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 57c1b58121..5a2630ecb0 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 493ff2dcde..2881162a34 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #if CONFIG(HAVE_ACPI_RESUME) diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index 8d4f855175..e3efd34529 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -18,11 +18,11 @@ #include #include #include +#include #include #include #include "pmic.h" -#include "reset.h" enum { MAX77620_I2C_ADDR = 0x3c diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 75075ad6fd..d9dacb7d08 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -18,11 +18,11 @@ #include #include #include +#include #include #include #include "pmic.h" -#include "reset.h" enum { MAX77620_I2C_ADDR = 0x3c, diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index 86834bfd71..80fe7e8266 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index 18047f28f9..1107b1a6a4 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index 73f57d15ec..91396b0074 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index d7892784ee..e466eb87aa 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -17,7 +17,6 @@ #include #include -#include #include #include #include diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 5b49ebffb7..8f8165a7c5 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c index 066155e08e..f8fa8d499e 100644 --- a/src/soc/cavium/common/bdk-coreboot.c +++ b/src/soc/cavium/common/bdk-coreboot.c @@ -22,7 +22,6 @@ #include #include #include -#include #include // BDK diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index ca1eb40236..ae2eac8e20 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 61ad7edb74..9dbfbd47ee 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index b471e5cf08..5351a0162f 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -27,7 +27,6 @@ #include #include #include -#include /* * check for a warm reset and do a hard reset instead. diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index ac43c27071..d8188f6924 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index f71f453bee..c3a4d41c8e 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -20,7 +20,7 @@ #include #include #include -#include + #include "hudson.h" void hudson_pci_port80(void) diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index abfa897752..34a3513b63 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -22,7 +22,7 @@ #include #include #include -#include + #include "hudson.h" #include "pci_devs.h" #include diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 3b801bafe8..1c248835ef 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -25,7 +25,6 @@ #include #include -#include #include "sb700.h" #include "smbus.h" diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index c1670c65a2..1e357df85a 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -17,7 +17,9 @@ */ #include +#include #include + #include "ck804.h" /* Someone messed up and snuck in some K8-specific code */ -- cgit v1.2.3