From e8a3af10691a4831a85d8760f7fcb20f78065f78 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 19 Nov 2022 18:39:22 +0200 Subject: sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tree is inconsistent with the use of TCO register space offsets and related preprocessor defines. The legacy space was offset from ACPI PM base by 0x60, but this changed with later platforms. The convenient way is to define the TCO registers relative to its base address and subtract 0x60 here, but this change cannot be easily done tree-wide or in one go. For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until all platforms use a clean style of tco_{read,write} accessor functions instead of {read,write}_pmbase16(), or worse, inw/outl(). Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas Reviewed-by: Angel Pons --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/include/soc/pm.h | 3 +++ src/soc/intel/braswell/Kconfig | 1 + src/soc/intel/braswell/include/soc/pm.h | 3 +++ src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/broadwell/include/soc/pm.h | 3 +++ src/soc/intel/broadwell/pch/Kconfig | 1 + src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/bd82x6x/pch.h | 2 ++ src/southbridge/intel/common/Kconfig.common | 3 +++ src/southbridge/intel/common/pmutil.h | 2 ++ src/southbridge/intel/common/tco.h | 8 ++++++++ src/southbridge/intel/i82801dx/Kconfig | 1 + src/southbridge/intel/i82801dx/i82801dx.h | 2 ++ src/southbridge/intel/i82801gx/Kconfig | 1 + src/southbridge/intel/i82801gx/i82801gx.h | 3 +++ src/southbridge/intel/i82801ix/Kconfig | 1 + src/southbridge/intel/i82801jx/Kconfig | 1 + src/southbridge/intel/ibexpeak/Kconfig | 1 + src/southbridge/intel/ibexpeak/pch.h | 2 ++ src/southbridge/intel/lynxpoint/Kconfig | 1 + src/southbridge/intel/lynxpoint/pch.h | 3 +++ 22 files changed, 45 insertions(+) (limited to 'src') diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index c2d24b29c6..5ecfe3eac1 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -34,6 +34,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select TCO_SPACE_NOT_YET_SPLIT config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h index dc8a7fadcd..1db5038673 100644 --- a/src/soc/intel/baytrail/include/soc/pm.h +++ b/src/soc/intel/baytrail/include/soc/pm.h @@ -222,6 +222,8 @@ # define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ #define GPE_CTRL 0x40 #define PM2A_CNT_BLK 0x50 + +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO_RLD 0x60 #define TCO_STS 0x64 # define SECOND_TO_STS (1 << 17) @@ -230,6 +232,7 @@ # define TCO_LOCK (1 << 12) # define TCO_TMR_HALT (1 << 11) #define TCO_TMR 0x70 +#endif /* I/O ports */ #define RST_CNT 0xcf9 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index f297b8f7a3..c35fa7473d 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT select NO_CBFS_MCACHE + select TCO_SPACE_NOT_YET_SPLIT config DCACHE_BSP_STACK_SIZE hex diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 6cb8d55873..131a996919 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -184,6 +184,8 @@ # define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ #define GPE_CTRL 0x40 #define PM2A_CNT_BLK 0x50 + +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO_RLD 0x60 #define TCO_STS 0x64 # define SECOND_TO_STS (1 << 17) @@ -192,6 +194,7 @@ # define TCO_LOCK (1 << 12) # define TCO_TMR_HALT (1 << 11) #define TCO_TMR 0x70 +#endif #if !defined(__ASSEMBLER__) && !defined(__ACPI__) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5b73f4f941..3878f142a7 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -12,6 +12,7 @@ config SOC_SPECIFIC_OPTIONS select INTEL_GMA_ACPI select MRC_SETTINGS_PROTECT select REG_SCRIPT + select TCO_SPACE_NOT_YET_SPLIT config BROADWELL_LPDDR3 bool diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 52fd364430..8bbc2de472 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -53,12 +53,15 @@ #define SWGPE_CTRL (1 << 1) #define DEVACT_STS 0x44 #define PM2_CNT 0x50 + +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_CNT 0x60 #define TCO_TMR_HLT (1 << 11) #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 #define TCO2_STS_SECOND_TO (1 << 1) +#endif #define GPE0_REG_MAX 4 #define GPE0_REG_SIZE 32 diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig index 4e187ff114..4800f3f804 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/soc/intel/broadwell/pch/Kconfig @@ -23,6 +23,7 @@ config PCH_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SPI_FLASH + select TCO_SPACE_NOT_YET_SPLIT config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 168c18e26c..7fee1f1680 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -36,6 +36,7 @@ config SOUTH_BRIDGE_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select TCO_SPACE_NOT_YET_SPLIT config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 2ebec62300..b5e05f6578 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -464,6 +464,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_STS 0x64 #define TCO1_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) @@ -473,6 +474,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define TCO_TMR_HLT (1 << 11) #define TCO_LOCK (1 << 12) #define TCO2_CNT 0x6a +#endif #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ diff --git a/src/southbridge/intel/common/Kconfig.common b/src/southbridge/intel/common/Kconfig.common index 5d7a4ee784..0caf96437f 100644 --- a/src/southbridge/intel/common/Kconfig.common +++ b/src/southbridge/intel/common/Kconfig.common @@ -103,6 +103,9 @@ config INTEL_CHIPSET_LOCKDOWN and S3 resume (always done by coreboot). Select this to let coreboot to do this on normal boot path. +config TCO_SPACE_NOT_YET_SPLIT + bool + config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG bool depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 5cf76b689f..744b1c1c8c 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -104,6 +104,7 @@ #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define BOOT_STS (1 << 18) @@ -111,6 +112,7 @@ #define TCO1_CNT 0x68 #define TCO_LOCK (1 << 12) #define TCO2_CNT 0x6a +#endif u16 get_pmbase(void); diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 03d312271e..4c3f6391b4 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -3,7 +3,15 @@ #ifndef SOUTHBRIDGE_INTEL_COMMON_TCO_H #define SOUTHBRIDGE_INTEL_COMMON_TCO_H +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) +/* Could get conflicting values. */ +#undef TCO1_STS +#undef TCO2_STS +#undef TCO1_CNT +#endif + #define PMBASE_TCO_OFFSET 0x60 + #define TCO1_STS 0x04 #define TCO1_TIMEOUT (1 << 3) #define TCO2_STS 0x06 diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 391a59fc6b..3916b414ba 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -13,6 +13,7 @@ config SOUTHBRIDGE_INTEL_I82801DX select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select BOOT_DEVICE_NOT_SPI_FLASH + select TCO_SPACE_NOT_YET_SPLIT if SOUTHBRIDGE_INTEL_I82801DX diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 4c1366e8c5..99f3af3305 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -140,8 +140,10 @@ void i82801dx_lpc_setup(void); #define DEVACT_STS 0x44 #define SS_CNT 0x50 +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) /* TCO1 Control Register */ #define TCO1_CNT 0x68 +#endif #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 9e7259f121..b1b885b2e5 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -22,6 +22,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_HPET + select TCO_SPACE_NOT_YET_SPLIT if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index ee34f74267..7088b64b38 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -323,7 +323,10 @@ void ich7_setup_cir(void); #define DEVACT_STS 0x44 #define SS_CNT 0x50 #define C3_RES 0x54 + +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_CNT 0x68 +#endif #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 0b4501627c..4d6b097bd6 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -20,6 +20,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select TCO_SPACE_NOT_YET_SPLIT select USE_WATCHDOG_ON_BOOT if SOUTHBRIDGE_INTEL_I82801IX diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 13357c7238..b18985231b 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_INTEL_I82801JX select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select TCO_SPACE_NOT_YET_SPLIT select USE_WATCHDOG_ON_BOOT if SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index a79b3f73af..fd5e32244b 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -32,6 +32,7 @@ config SOUTH_BRIDGE_OPTIONS select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select TCO_SPACE_NOT_YET_SPLIT config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index c42fe0fbd7..5371641b6e 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -445,9 +445,11 @@ void pch_enable(struct device *dev); #define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 +#endif #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index b188251d8b..ecfdea2aae 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -34,6 +34,7 @@ config SOUTH_BRIDGE_OPTIONS select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select TCO_SPACE_NOT_YET_SPLIT config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index dcd3ce545e..0d8be7bd9b 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -619,10 +619,13 @@ void mainboard_config_rcba(void); #define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 #define SECOND_TO_STS (1 << 1) +#endif + #define ALT_GP_SMI_EN2 0x5c #define ALT_GP_SMI_STS2 0x5e -- cgit v1.2.3