From e81560c6cf1980144dbb5e15c108db36eae97ce9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 25 Nov 2021 13:15:07 +0100 Subject: mb/prodrive/hermes: Get rid of variant structure There's no need to use a variant structure here. Only one variant is used, and revision-specific differences are handled at run-time, and it's unlikely that another variant will ever exist. Reorganize the mainboard code to get rid of the variant structure. Change-Id: I1543f5b76975b0e7183fbb759e9bae5c34151d06 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/59671 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/prodrive/hermes/Kconfig | 3 - src/mainboard/prodrive/hermes/Makefile.inc | 10 +- src/mainboard/prodrive/hermes/board_info.txt | 2 + src/mainboard/prodrive/hermes/bootblock.c | 3 +- src/mainboard/prodrive/hermes/data.vbt | Bin 0 -> 4608 bytes src/mainboard/prodrive/hermes/eeprom.c | 2 +- src/mainboard/prodrive/hermes/eeprom.h | 121 ++++++ src/mainboard/prodrive/hermes/gpio.c | 415 +++++++++++++++++++++ src/mainboard/prodrive/hermes/gpio.h | 9 + src/mainboard/prodrive/hermes/hda_verb.c | 131 ++++++- src/mainboard/prodrive/hermes/mainboard.c | 6 +- src/mainboard/prodrive/hermes/memory.c | 44 --- src/mainboard/prodrive/hermes/ramstage.c | 5 +- src/mainboard/prodrive/hermes/romstage.c | 41 +- src/mainboard/prodrive/hermes/smbios.c | 2 +- .../hermes/variants/baseboard/Makefile.inc | 4 - .../hermes/variants/baseboard/board_info.txt | 7 - .../prodrive/hermes/variants/baseboard/data.vbt | Bin 4608 -> 0 bytes .../prodrive/hermes/variants/baseboard/gpio.c | 414 -------------------- .../prodrive/hermes/variants/baseboard/hda_verb.c | 65 ---- .../hermes/variants/baseboard/include/eeprom.h | 121 ------ .../variants/baseboard/include/variant/gpio.h | 9 - .../variants/baseboard/include/variant/variants.h | 9 - .../prodrive/hermes/variants/r04/hda_verb.c | 73 ---- 24 files changed, 728 insertions(+), 768 deletions(-) create mode 100644 src/mainboard/prodrive/hermes/data.vbt create mode 100644 src/mainboard/prodrive/hermes/eeprom.h create mode 100644 src/mainboard/prodrive/hermes/gpio.c create mode 100644 src/mainboard/prodrive/hermes/gpio.h delete mode 100644 src/mainboard/prodrive/hermes/memory.c delete mode 100644 src/mainboard/prodrive/hermes/variants/baseboard/Makefile.inc delete mode 100644 src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt delete mode 100644 src/mainboard/prodrive/hermes/variants/baseboard/data.vbt delete mode 100644 src/mainboard/prodrive/hermes/variants/baseboard/gpio.c delete mode 100644 src/mainboard/prodrive/hermes/variants/baseboard/hda_verb.c delete mode 100644 src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h delete mode 100644 src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h delete mode 100644 src/mainboard/prodrive/hermes/variants/baseboard/include/variant/variants.h delete mode 100644 src/mainboard/prodrive/hermes/variants/r04/hda_verb.c (limited to 'src') diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig index af07ee10c8..ae7b5f1269 100644 --- a/src/mainboard/prodrive/hermes/Kconfig +++ b/src/mainboard/prodrive/hermes/Kconfig @@ -45,9 +45,6 @@ config PCIEXP_CLK_PM bool default n -config VARIANT_DIR - default "baseboard" if BOARD_PRODRIVE_HERMES_BASEBOARD - config MAX_CPUS int default 16 diff --git a/src/mainboard/prodrive/hermes/Makefile.inc b/src/mainboard/prodrive/hermes/Makefile.inc index d13b50aff7..caaddec7be 100644 --- a/src/mainboard/prodrive/hermes/Makefile.inc +++ b/src/mainboard/prodrive/hermes/Makefile.inc @@ -1,16 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-or-later -subdirs-y += variants/$(VARIANT_DIR) -CPPFLAGS_common += -I$(src)/mainboard/prodrive/hermes/variants/$(VARIANT_DIR)/include - bootblock-y += bootblock.c -romstage-y += memory.c +bootblock-y += gpio.c + romstage-y += eeprom.c +ramstage-y += gpio.c ramstage-y += ramstage.c ramstage-y += mainboard.c ramstage-y += eeprom.c ramstage-y += smbios.c - -ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += variants/baseboard/hda_verb.c -ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += variants/r04/hda_verb.c diff --git a/src/mainboard/prodrive/hermes/board_info.txt b/src/mainboard/prodrive/hermes/board_info.txt index 72bcfa956f..3a5aff454c 100644 --- a/src/mainboard/prodrive/hermes/board_info.txt +++ b/src/mainboard/prodrive/hermes/board_info.txt @@ -1,5 +1,7 @@ Category: server Vendor name: Prodrive +Board name: Hermes +Board URL: https://prodrive-technologies.com/products/embedded-computing-systems/motherboards/hermes-8th-9th-gen-series/ ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/prodrive/hermes/bootblock.c b/src/mainboard/prodrive/hermes/bootblock.c index 40fd0b48a3..9db1fa8306 100644 --- a/src/mainboard/prodrive/hermes/bootblock.c +++ b/src/mainboard/prodrive/hermes/bootblock.c @@ -2,8 +2,9 @@ #include #include +#include #include -#include + #include "gpio.h" void bootblock_mainboard_early_init(void) diff --git a/src/mainboard/prodrive/hermes/data.vbt b/src/mainboard/prodrive/hermes/data.vbt new file mode 100644 index 0000000000..66c5f6ee5c Binary files /dev/null and b/src/mainboard/prodrive/hermes/data.vbt differ diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index cdea67d6d3..006f922496 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -9,7 +9,7 @@ #include #include -#include "variants/baseboard/include/eeprom.h" +#include "eeprom.h" #define I2C_ADDR_EEPROM 0x57 diff --git a/src/mainboard/prodrive/hermes/eeprom.h b/src/mainboard/prodrive/hermes/eeprom.h new file mode 100644 index 0000000000..0d4e9d8e31 --- /dev/null +++ b/src/mainboard/prodrive/hermes/eeprom.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +union eeprom_dimm_layout { + struct __packed { + char name[50]; + char manufacturer[50]; + uint8_t ranks; + uint8_t controller_id; + uint8_t data_width_bits; + uint8_t bus_width_bits; + uint32_t capacity_mib; + uint32_t max_tdp_milliwatts; + }; + uint8_t raw[0x80]; +}; + +_Static_assert(sizeof(union eeprom_dimm_layout) == 0x80, + "union eeprom_dimm_layout has invalid size!"); + +struct __packed eeprom_board_layout { + uint32_t signature; + union { + struct __packed { + char cpu_name[50]; + uint8_t cpu_count; + uint32_t cpu_max_non_turbo_frequency; + char pch_name[50]; + union eeprom_dimm_layout dimm[4]; + }; + uint8_t raw_layout[617]; + }; +}; + +_Static_assert(sizeof(struct eeprom_board_layout) == (617 + sizeof(uint32_t)), + "struct eeprom_board_layout has invalid size!"); + +struct __packed eeprom_board_settings { + uint32_t signature; + union { + struct __packed { + uint8_t secureboot; + uint8_t primary_video; + uint8_t deep_sx_enabled; + uint8_t wake_on_usb; + uint8_t usb_powered_in_s5; + uint8_t power_state_after_g3; + uint8_t blue_rear_vref; + uint8_t front_panel_audio; + uint8_t pxe_boot_capability; + }; + uint8_t raw_settings[9]; + }; +}; + +_Static_assert(sizeof(struct eeprom_board_settings) == (9 + sizeof(uint32_t)), + "struct eeprom_board_settings has invalid size!"); + +struct __packed eeprom_bmc_settings { + uint8_t pcie_mux; + uint8_t hsi; +}; + +#define HERMES_SERIAL_NUMBER_LENGTH 32 + +/* The EEPROM on address 0x57 has the following vendor defined layout: */ +struct __packed eeprom_layout { + union { + uint8_t RawFSPMUPD[0x600]; + FSPM_UPD mupd; + }; + union { + uint8_t RawFSPSUPD[0xC00]; + FSPS_UPD supd; + }; + union { + uint8_t RawBoardLayout[0x400]; + struct eeprom_board_layout BoardLayout; + }; + char system_serial_number[HERMES_SERIAL_NUMBER_LENGTH]; + char board_serial_number[HERMES_SERIAL_NUMBER_LENGTH]; + uint8_t BootOrder[0x8c0]; + union { + uint8_t RawBoardSetting[0xF8]; + struct eeprom_board_settings BoardSettings; + }; + union { + uint8_t RawBMCSetting[0x8]; + struct eeprom_bmc_settings BMCSettings; + }; +}; + +_Static_assert(sizeof(FSPM_UPD) <= 0x600, "FSPM_UPD too big"); +_Static_assert(sizeof(FSPS_UPD) <= 0xC00, "FSPS_UPD too big"); +_Static_assert(sizeof(struct eeprom_layout) == 0x2000, "EEPROM layout size mismatch"); + +bool eeprom_read_buffer(void *blob, size_t read_offset, size_t size); +int check_signature(const size_t offset, const uint64_t signature); +struct eeprom_board_settings *get_board_settings(void); +struct eeprom_bmc_settings *get_bmc_settings(void); +uint8_t get_bmc_hsi(void); +void report_eeprom_error(const size_t off); +bool write_board_settings(const struct eeprom_board_layout *new_layout); + +#define READ_EEPROM(section_type, section_name, dest, opt_name) \ + do { \ + typeof(dest->opt_name) __tmp; \ + size_t __off = offsetof(struct eeprom_layout, section_name); \ + bool ret = eeprom_read_buffer(&__tmp, \ + __off + offsetof(section_type, opt_name), \ + sizeof(__tmp)); \ + if (ret) { \ + report_eeprom_error(__off + offsetof(section_type, opt_name)); \ + } else { \ + dest->opt_name = __tmp; \ + } \ + } while (0) + +#define READ_EEPROM_FSP_M(dest, opt_name) READ_EEPROM(FSPM_UPD, RawFSPMUPD, dest, opt_name) +#define READ_EEPROM_FSP_S(dest, opt_name) READ_EEPROM(FSPS_UPD, RawFSPSUPD, dest, opt_name) diff --git a/src/mainboard/prodrive/hermes/gpio.c b/src/mainboard/prodrive/hermes/gpio.c new file mode 100644 index 0000000000..97e6740594 --- /dev/null +++ b/src/mainboard/prodrive/hermes/gpio.c @@ -0,0 +1,415 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include "gpio.h" + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPP_A ------- */ + + /* ISH */ + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_B ------- */ + PAD_NC(GPP_B0, NONE), + PAD_NC(GPP_B1, NONE), + + /* GPP_B2 - M2_E_BT_UART_WAKE_n */ + PAD_CFG_GPI_INT(GPP_B2, NONE, DEEP, OFF), + + /* GPP_B3 - PCH_M2_E_BT_KILL_n : handled at runtime */ + /* GPP_B4 - PCH_M2_E_WLAN_KILL_n : handled at runtime */ + + /* SRCCLKREQ0# - SRCCLKREQ5# */ + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* M2_M_CLK_REQ_n */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* M2_E_CLK_REQ_n */ + + PAD_NC(GPP_B11, NONE), + + /* GPP_B12 - SLP_S0_n */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 - PLTRST_n */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + + /* GSPI0 */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* SPI0_CS */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* SPI0_CLK */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* SPI0_MISO */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* SPI0_MOSI */ + + /* GSPI1 */ + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), /* PCH_SML1_ALERT_n */ + + /* ------- GPIO Group GPP_C ------- */ + /* SML0 - Used by CSME */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PCH_SML0_CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PCH_SML0_DATA */ + PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), /* PCH_SML0_ALERT_N */ + + /* SML1 - Used by CSME */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PCH_SML1_CLK */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PCH_SML1_DATA */ + + /* UART0 */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* UART0_RTS_N */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* UART0_CTS_N */ + + /* UART1 */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* UART1_RTS_N */ + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* UART1_CTS_N */ + + PAD_NC(GPP_C17, NONE), + + PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), /* AUD_FPA_PRSNT_n */ + /* GPP_C19 - AUD_AMP_EN : configured at runtime */ + + /* UART2 */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* UART2_RTS_N */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* UART2_CTS_N */ + + /* ------- GPIO Group GPP_D ------- */ + /* SPI1 */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + + PAD_NC(GPP_D4, NONE), + + /* CNVi */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), /* M2_E_BT_PCMFRM_CRF_RST_n */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), /* M2_E_BT_PCMOUT_CLKREQ0 */ + PAD_NC(GPP_D7, NONE), /* M2_E_BT_PCMIN */ + PAD_NC(GPP_D8, NONE), /* M2_E_BT_PCMCLK */ + + /* ISH SPI */ + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + + /* ISH UART */ + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + + /* DMIC */ + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + /* GPP_G0 - USB31_RP1_PWR_EN : configured at runtime */ + /* GPP_G1 - USB31_RP2_PWR_EN : configured at runtime */ + /* GPP_G2 - USB31_FP_PWR_EN : configured at runtime */ + /* GPP_G3 - USB2_FP1_PWR_EN : configured at runtime */ + /* GPP_G4 - USB2_FP2_PWR_EN : configured at runtime */ + + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + + /* ------- GPIO Group GPD ------- */ + /* GPD0 - BATLOW */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + /* GPD3 - PRWBTN# */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7 - GPIO */ + PAD_NC(GPD7, NONE), + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9 - SLP_WLAN */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11 - LAN_DISABLE_n */ + PAD_CFG_NF(GPD11, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_K ------- */ + /* GPP_K0 - PERST_PCH_SLOTS_n : configured at runtime */ + /* GPP_K1 - PERST_CPU_SLOTS_n : configured at runtime */ + /* GPP_K2 - PERST_CNVI_SLOTS_n : configured at runtime */ + /* GPP_K3 - DP1_PWR_EN : configured at runtime */ + /* GPP_K4 - DP2_PWR_EN : configured at runtime */ + /* GPP_K5 - DP3_PWR_EN : configured at runtime */ + + PAD_NC(GPP_K6, NONE), + + /* GPP_K7 - EN_3V3_KEYM_PCH : configured at runtime */ + + PAD_NC(GPP_K8, NONE), + PAD_NC(GPP_K9, NONE), + PAD_NC(GPP_K10, NONE), + PAD_NC(GPP_K11, NONE), + + /* K12 - K16 in early GPIO config */ + + PAD_NC(GPP_K17, NONE), + + /* GPP_K18/!NMI - NC */ + PAD_NC(GPP_K18, NONE), + /* GPP_K19/!SMI - NC */ + PAD_NC(GPP_K19, NONE), + + /* GPP_K20 - CPU_CATERR_PCH_n */ + PAD_CFG_GPI(GPP_K20, NONE, DEEP), + /* GPP_K21 - TPM_INT_n */ + PAD_CFG_GPI_INT(GPP_K21, NONE, DEEP, OFF), /* Trigger? */ + /* GPP_K22 - NC */ + PAD_NC(GPP_K22, NONE), + /* GPP_K23 - NC */ + PAD_NC(GPP_K23, NONE), + + /* ------- GPIO Group GPP_H ------- */ + + /* SRCCLKREQ6# - SRCCLKREQ10# not used as CLKREQ, external 10K pullup */ + PAD_CFG_GPI(GPP_H0, NONE, DEEP), /* PCIE_SLOT1_PRSNT_PCH_n */ + PAD_CFG_GPI(GPP_H1, NONE, DEEP), /* PCIE_SLOT2_PRSNT_PCH_n */ + PAD_CFG_GPI(GPP_H2, NONE, DEEP), /* PCIE_SLOT3_PRSNT_PCH_n */ + PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* PCIE_SLOT4_PRSNT_PCH_n */ + PAD_CFG_GPI(GPP_H4, NONE, DEEP), /* PCIE_SLOT6_PRSNT_PCH_n */ + + PAD_CFG_GPI(GPP_H4, NONE, DEEP), /* PCIE_SLOT6_PRSNT_PCH_n */ + + /* GPP_H5 - PCH_HBLED_n configured in early init */ + + /* SRCCLKREQ13# - SRCCLKREQ15# */ + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + + /* SML2 - Used by CSME */ + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + + /* SML3 - Used by CSME */ + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + + /* SML4 - Used by CSME */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), /* PCIE_SMB_CLK */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* PCIE_SMB_DATA */ + PAD_NC(GPP_H18, NONE), + + /* ISH I2C0 */ + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + + /* ISH I2C1 */ + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + /* GPP_E0 - NC */ + PAD_NC(GPP_E0, NONE), + /* GPP_E1 - M2_SATA_PCIE_SEL */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* GPP_E2 - NC */ + PAD_NC(GPP_E2, NONE), + /* GPP_E3 - NC */ + PAD_NC(GPP_E3, NONE), + /* GPP_E4 - NC */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E5 - PCH_M2_SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* GPP_E6 - NC */ + PAD_NC(GPP_E6, NONE), + /* GPP_E8 - SATALED# */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* GPP_E9 - USB31_RP1_OC_N */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* GPP_E10 - USB31_RP2_OC_N */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* GPP_E11 - USB31_FP_OC_N */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* GPP_E12 - USB2_FP1_OC_N */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_F ------- */ + /* SATAGP3-7 */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + + /* SATA DEVSLP3-7 */ + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + + /* SGPIO has external 2K pullups */ + /* GPP_F10 - SATA_SCLOCK */ + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + /* GPP_F11 - SATA_SLOAD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* GPP_F12 - SATA_SDATAOUT1 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* GPP_F13 - SATA_BMC_SDATAOUT0 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + + /* GPP_F14 - PS_ON_PCH_n */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF2), + /* GPP_F15 - USB2_FP2_OC_N */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + + /* GPP_F16 - NC/PU */ + PAD_NC(GPP_F16, NONE), + /* GPP_F17 - GPIO */ + PAD_NC(GPP_F17, NONE), + /* GPP_F18 - GPIO */ + PAD_NC(GPP_F18, NONE), + /* GPP_F19 - GPIO */ + PAD_NC(GPP_F19, NONE), + /* GPP_F20 - GPIO */ + PAD_NC(GPP_F20, NONE), + /* GPP_F21 - GPIO */ + PAD_NC(GPP_F21, NONE), + /* GPP_F22 - GPIO */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23 - NC */ + PAD_NC(GPP_F23, NONE), + /* GPP_J0 - CNV_GNSS_PA_BLANKING */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), + /* GPP_J1 - NC */ + PAD_NC(GPP_J1, NONE), + /* GPP_J2 - NC */ + PAD_NC(GPP_J2, NONE), + /* GPP_J3 - NC */ + PAD_NC(GPP_J3, NONE), + + /* CNVi */ + /* GPP_J4 - CNV_BRI_DT*/ + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), + /* GPP_J5 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), + /* GPP_J6 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), + /* GPP_J7 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), + /* GPP_J8 - CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), + /* GPP_J9 - CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), + + PAD_NC(GPP_J10, NONE), + PAD_NC(GPP_J11, NONE), + + /* Display Port */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* DP1_HPD */ + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), /* DP2_HPD */ + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), /* DP3_HPD */ + PAD_NC(GPP_I3, NONE), + PAD_NC(GPP_I4, NONE), + + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), /* DP1_DDC_SCL */ + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), /* DP1_DDC_SDA */ + + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* DP2_DDC_SCL */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* DP2_DDC_SDA */ + + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* DP3_DDC_SCL */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* DP3_DDC_SDA */ + + PAD_NC(GPP_I11, NONE), + PAD_NC(GPP_I12, NONE), + PAD_NC(GPP_I13, NONE), + PAD_NC(GPP_I14, NONE), + +}; + +/* Early pad configuration in bootblock. */ +const struct pad_config early_gpio_table[] = { + /* Get PCIe out of reset */ + PAD_CFG_GPO(GPP_K0, 1, DEEP), /* PERST_PCH_SLOTS_n */ + PAD_CFG_GPO(GPP_K1, 1, DEEP), /* PERST_CPU_SLOTS_n */ + PAD_CFG_GPO(GPP_K2, 1, DEEP), /* PERST_CNVI_SLOTS_n */ + + /* SMB */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_SMB_CLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_SMB_DATA */ + PAD_NC(GPP_C2, NONE), + + /* BMC HSI */ + PAD_CFG_GPI(GPP_K12, NONE, DEEP), /* PCH_IO_2 */ + PAD_CFG_GPI(GPP_K13, NONE, DEEP), /* PCH_IO_3 */ + PAD_CFG_GPI(GPP_K14, NONE, DEEP), /* PCH_IO_1 */ + PAD_NC(GPP_K15, NONE), + PAD_CFG_GPI(GPP_K16, NONE, DEEP), /* PCH_IO_0 */ + + /* LED */ + PAD_CFG_GPO(GPP_H5, 0, DEEP), /* PCH_HBLED_n */ + + /* UART0 */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ + + /* UART1 */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */ + + /* UART2 */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ +}; + +void program_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +void program_early_gpio_pads(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/prodrive/hermes/gpio.h b/src/mainboard/prodrive/hermes/gpio.h new file mode 100644 index 0000000000..8fce3c8b39 --- /dev/null +++ b/src/mainboard/prodrive/hermes/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef PCH_GPIO_H +#define PCH_GPIO_H + +void program_gpio_pads(void); +void program_early_gpio_pads(void); + +#endif /* PCH_GPIO_H */ diff --git a/src/mainboard/prodrive/hermes/hda_verb.c b/src/mainboard/prodrive/hermes/hda_verb.c index 9780e7dcb5..06f2289880 100644 --- a/src/mainboard/prodrive/hermes/hda_verb.c +++ b/src/mainboard/prodrive/hermes/hda_verb.c @@ -2,10 +2,135 @@ #include #include -#include -#include "variants/baseboard/include/eeprom.h" -#include "variants/baseboard/include/variant/variants.h" +#include "eeprom.h" + +const u32 cim_verb_data[] = { + 0x10ec0888, /* Codec Vendor / Device ID: Realtek ALC888 */ + 0x10ec0888, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1d336700), + + /* Pin widgets */ + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), /* SPDIF-OUT2 - disabled */ + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), /* digital MIC - disabled */ + AZALIA_PIN_CFG(0, 0x14, 0x01014430), /* PORT D - rear line out */ + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), /* PORT G - disabled */ + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), /* PORT H - disabled */ + AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), /* PORT B - rear mic in */ + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), /* CD audio - disabled */ + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), /* BEEPIN */ + AZALIA_PIN_CFG(0, 0x1e, 0x01452160), /* SPDIF-OUT */ + AZALIA_PIN_CFG(0, 0x1f, 0x01C52170), /* SPDIF-IN */ + + /* Config for R02 and older */ + AZALIA_PIN_CFG(0, 0x19, 0x02214c40), /* port F - front hp out */ + AZALIA_PIN_CFG(0, 0x1a, 0x901001f0), /* port C - internal speaker */ + AZALIA_PIN_CFG(0, 0x1b, 0x01813c10), /* port E - rear line in/mic - Blue */ + AZALIA_PIN_CFG(0, 0x15, 0x02a19c20), /* port A - audio hdr input */ + + /* + * VerbTable: CFL Display Audio Codec + * Revision ID = 0xFF + * Codec Vendor: 0x8086280B + */ + 0x8086280B, + 0xFFFFFFFF, + 5, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + /* + * Display Audio Verb Table + * For GEN9, the Vendor Node ID is 08h + * Port to be exposed to the inbox driver in the vanilla mode + * PORT C - BIT[7:6] = 01b + */ + 0x20878101, + + /* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */ + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + /* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */ + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + /* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */ + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + /* Disable the third converter and third Pin (NID 08h) */ + 0x20878100, + + /* Dummy entries */ + 0x20878100, + 0x20878100, +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; + +static const u32 r04_verb_data[] = { + AZALIA_PIN_CFG(0, 0x19, 0x02a19c20), /* PORT F - front mic in */ + AZALIA_PIN_CFG(0, 0x1a, 0x01813c51), /* PORT C - rear line in (mic support) */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), /* PORT E - disabled */ + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), /* PORT A - disabled */ +}; + +static u32 get_port_c_vref_cfg(uint8_t blue_rear_vref) +{ + switch (blue_rear_vref) { + default: + case 0: + return 0x02040000; + case 1: + return 0x02041000; + case 2: + return 0x02044000; + case 3: + return 0x02045000; + case 4: + return 0x02046000; + } +} + +static u32 get_front_panel_cfg(uint8_t front_panel_audio) +{ + switch (front_panel_audio) { + default: + case 0: + return AZALIA_PIN_CFG_NC(0); + case 1: + return 0x022a4c40; + case 2: + return AZALIA_PIN_DESC( + INTEGRATED, + INTERNAL, + NA, + SPEAKER, + TYPE_UNKNOWN, + COLOR_UNKNOWN, + false, + 0xf, + 0); + } +} + +static void mainboard_r0x_configure_alc888(u8 *base, u32 viddid) +{ + /* Overwrite settings made by baseboard */ + azalia_program_verb_table(base, r04_verb_data, ARRAY_SIZE(r04_verb_data)); + + const struct eeprom_board_settings *const board_cfg = get_board_settings(); + + if (!board_cfg) + return; + + const u32 front_panel_cfg = get_front_panel_cfg(board_cfg->front_panel_audio); + + const u32 verbs[] = { + AZALIA_PIN_CFG(0, 0x1b, front_panel_cfg), + 0x0205000d, /* Pin 37 vrefo hidden register - used as port C vref */ + get_port_c_vref_cfg(board_cfg->blue_rear_vref), + }; + azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs)); +} void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) { diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index 6ae6b89104..1155b96944 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -8,10 +8,14 @@ #include #include #include +#include +#include #include +#include #include #include -#include "variants/baseboard/include/eeprom.h" + +#include "eeprom.h" #include "gpio.h" /* FIXME: Example code below */ diff --git a/src/mainboard/prodrive/hermes/memory.c b/src/mainboard/prodrive/hermes/memory.c deleted file mode 100644 index 0ff21c4754..0000000000 --- a/src/mainboard/prodrive/hermes/memory.c +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -static const struct cnl_mb_cfg baseboard_memcfg_cfg = { - /* Access memory info through SMBUS. */ - .spd[0] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xA0} - }, - .spd[1] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xA2} - }, - .spd[2] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xA4} - }, - .spd[3] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xA6} - }, - - /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = {121, 81, 100}, - - /* Baseboard Rcomp target values. */ - .rcomp_targets = {100, 40, 20, 20, 26}, - - /* Baseboard is an interleaved design */ - .dq_pins_interleaved = 1, - - /* Baseboard is using config 2 for vref_ca */ - .vref_ca_config = 2, - - /* Disable Early Command Training */ - .ect = 0, -}; - -const struct cnl_mb_cfg *variant_memcfg_config(void) -{ - return &baseboard_memcfg_cfg; -} diff --git a/src/mainboard/prodrive/hermes/ramstage.c b/src/mainboard/prodrive/hermes/ramstage.c index 917f3b93cf..f38ee379d1 100644 --- a/src/mainboard/prodrive/hermes/ramstage.c +++ b/src/mainboard/prodrive/hermes/ramstage.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include "variants/baseboard/include/eeprom.h" + +#include "eeprom.h" +#include "gpio.h" void mainboard_silicon_init_params(FSPS_UPD *supd) { diff --git a/src/mainboard/prodrive/hermes/romstage.c b/src/mainboard/prodrive/hermes/romstage.c index 238a7919a1..32b4c76347 100644 --- a/src/mainboard/prodrive/hermes/romstage.c +++ b/src/mainboard/prodrive/hermes/romstage.c @@ -2,14 +2,49 @@ #include #include -#include -#include "variants/baseboard/include/eeprom.h" + +#include "eeprom.h" + +static const struct cnl_mb_cfg baseboard_mem_cfg = { + /* Access memory info through SMBUS. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA0} + }, + .spd[1] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA2} + }, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA4} + }, + .spd[3] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xA6} + }, + + /* Baseboard uses 121, 81 and 100 rcomp resistors */ + .rcomp_resistor = {121, 81, 100}, + + /* Baseboard Rcomp target values. */ + .rcomp_targets = {100, 40, 20, 20, 26}, + + /* Baseboard is an interleaved design */ + .dq_pins_interleaved = 1, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Disable Early Command Training */ + .ect = 0, +}; void mainboard_memory_init_params(FSPM_UPD *memupd) { memupd->FspmConfig.UserBd = BOARD_TYPE_SERVER; memupd->FspmTestConfig.SmbusSpdWriteDisable = 0; - cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config()); + cannonlake_memcfg_init(&memupd->FspmConfig, &baseboard_mem_cfg); /* Overwrite memupd */ if (!check_signature(offsetof(struct eeprom_layout, mupd), FSPM_UPD_SIGNATURE)) diff --git a/src/mainboard/prodrive/hermes/smbios.c b/src/mainboard/prodrive/hermes/smbios.c index af81e86c9a..624549e90d 100644 --- a/src/mainboard/prodrive/hermes/smbios.c +++ b/src/mainboard/prodrive/hermes/smbios.c @@ -4,7 +4,7 @@ #include #include -#include "variants/baseboard/include/eeprom.h" +#include "eeprom.h" const char *smbios_system_serial_number(void) { diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/Makefile.inc b/src/mainboard/prodrive/hermes/variants/baseboard/Makefile.inc deleted file mode 100644 index cc5cdc1ace..0000000000 --- a/src/mainboard/prodrive/hermes/variants/baseboard/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -bootblock-y += gpio.c -ramstage-y += gpio.c diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt b/src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt deleted file mode 100644 index 009fbfd819..0000000000 --- a/src/mainboard/prodrive/hermes/variants/baseboard/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: server -Vendor name: Prodrive -Board name: Hermes -Board URL: https://prodrive-technologies.com/products/embedded-computing-systems/motherboards/hermes-8th-9th-gen-series/ -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/data.vbt b/src/mainboard/prodrive/hermes/variants/baseboard/data.vbt deleted file mode 100644 index 66c5f6ee5c..0000000000 Binary files a/src/mainboard/prodrive/hermes/variants/baseboard/data.vbt and /dev/null differ diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c deleted file mode 100644 index 7f81842e21..0000000000 --- a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c +++ /dev/null @@ -1,414 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "include/variant/gpio.h" -#include -#include -#include - -/* Pad configuration in ramstage */ -static const struct pad_config gpio_table[] = { - /* ------- GPIO Group GPP_A ------- */ - - /* ISH */ - PAD_NC(GPP_A17, NONE), - PAD_NC(GPP_A18, NONE), - PAD_NC(GPP_A19, NONE), - PAD_NC(GPP_A20, NONE), - PAD_NC(GPP_A21, NONE), - PAD_NC(GPP_A22, NONE), - PAD_NC(GPP_A23, NONE), - - /* ------- GPIO Group GPP_B ------- */ - PAD_NC(GPP_B0, NONE), - PAD_NC(GPP_B1, NONE), - - /* GPP_B2 - M2_E_BT_UART_WAKE_n */ - PAD_CFG_GPI_INT(GPP_B2, NONE, DEEP, OFF), - - /* GPP_B3 - PCH_M2_E_BT_KILL_n : handled at runtime */ - /* GPP_B4 - PCH_M2_E_WLAN_KILL_n : handled at runtime */ - - /* SRCCLKREQ0# - SRCCLKREQ5# */ - PAD_NC(GPP_B5, NONE), - PAD_NC(GPP_B6, NONE), - PAD_NC(GPP_B7, NONE), - PAD_NC(GPP_B8, NONE), - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* M2_M_CLK_REQ_n */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* M2_E_CLK_REQ_n */ - - PAD_NC(GPP_B11, NONE), - - /* GPP_B12 - SLP_S0_n */ - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - /* GPP_B13 - PLTRST_n */ - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - - /* GPP_B14 - SPKR */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), - - /* GSPI0 */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* SPI0_CS */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* SPI0_CLK */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* SPI0_MISO */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* SPI0_MOSI */ - - /* GSPI1 */ - PAD_NC(GPP_B19, NONE), - PAD_NC(GPP_B20, NONE), - PAD_NC(GPP_B21, NONE), - PAD_NC(GPP_B22, NONE), - - PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), /* PCH_SML1_ALERT_n */ - - /* ------- GPIO Group GPP_C ------- */ - /* SML0 - Used by CSME */ - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PCH_SML0_CLK */ - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PCH_SML0_DATA */ - PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), /* PCH_SML0_ALERT_N */ - - /* SML1 - Used by CSME */ - PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PCH_SML1_CLK */ - PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PCH_SML1_DATA */ - - /* UART0 */ - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ - PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* UART0_RTS_N */ - PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* UART0_CTS_N */ - - /* UART1 */ - PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */ - PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* UART1_RTS_N */ - PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* UART1_CTS_N */ - - PAD_NC(GPP_C17, NONE), - - PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), /* AUD_FPA_PRSNT_n */ - /* GPP_C19 - AUD_AMP_EN : configured at runtime */ - - /* UART2 */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ - PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* UART2_RTS_N */ - PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* UART2_CTS_N */ - - /* ------- GPIO Group GPP_D ------- */ - /* SPI1 */ - PAD_NC(GPP_D0, NONE), - PAD_NC(GPP_D1, NONE), - PAD_NC(GPP_D2, NONE), - PAD_NC(GPP_D3, NONE), - - PAD_NC(GPP_D4, NONE), - - /* CNVi */ - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), /* M2_E_BT_PCMFRM_CRF_RST_n */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), /* M2_E_BT_PCMOUT_CLKREQ0 */ - PAD_NC(GPP_D7, NONE), /* M2_E_BT_PCMIN */ - PAD_NC(GPP_D8, NONE), /* M2_E_BT_PCMCLK */ - - /* ISH SPI */ - PAD_NC(GPP_D9, NONE), - PAD_NC(GPP_D10, NONE), - PAD_NC(GPP_D11, NONE), - PAD_NC(GPP_D12, NONE), - - /* ISH UART */ - PAD_NC(GPP_D13, NONE), - PAD_NC(GPP_D14, NONE), - PAD_NC(GPP_D15, NONE), - PAD_NC(GPP_D16, NONE), - - /* DMIC */ - PAD_NC(GPP_D17, NONE), - PAD_NC(GPP_D18, NONE), - PAD_NC(GPP_D19, NONE), - PAD_NC(GPP_D20, NONE), - - PAD_NC(GPP_D21, NONE), - PAD_NC(GPP_D22, NONE), - PAD_NC(GPP_D23, NONE), - - /* ------- GPIO Group GPP_G ------- */ - /* GPP_G0 - USB31_RP1_PWR_EN : configured at runtime */ - /* GPP_G1 - USB31_RP2_PWR_EN : configured at runtime */ - /* GPP_G2 - USB31_FP_PWR_EN : configured at runtime */ - /* GPP_G3 - USB2_FP1_PWR_EN : configured at runtime */ - /* GPP_G4 - USB2_FP2_PWR_EN : configured at runtime */ - - PAD_NC(GPP_G5, NONE), - PAD_NC(GPP_G6, NONE), - PAD_NC(GPP_G7, NONE), - - /* ------- GPIO Group GPD ------- */ - /* GPD0 - BATLOW */ - PAD_CFG_NF(GPD0, NONE, DEEP, NF1), - /* GPD1 - ACPRESENT */ - PAD_CFG_NF(GPD1, NONE, DEEP, NF1), - /* GPD2 - LAN_WAKE# */ - PAD_CFG_NF(GPD2, NONE, DEEP, NF1), - /* GPD3 - PRWBTN# */ - PAD_CFG_NF(GPD3, NONE, DEEP, NF1), - /* GPD4 - SLP_S3# */ - PAD_CFG_NF(GPD4, NONE, DEEP, NF1), - /* GPD5 - SLP_S4# */ - PAD_CFG_NF(GPD5, NONE, DEEP, NF1), - /* GPD6 - SLP_A# */ - PAD_CFG_NF(GPD6, NONE, DEEP, NF1), - /* GPD7 - GPIO */ - PAD_NC(GPD7, NONE), - /* GPD8 - SUSCLK */ - PAD_CFG_NF(GPD8, NONE, DEEP, NF1), - /* GPD9 - SLP_WLAN */ - PAD_CFG_NF(GPD9, NONE, DEEP, NF1), - /* GPD10 - SLP_S5# */ - PAD_CFG_NF(GPD10, NONE, DEEP, NF1), - /* GPD11 - LAN_DISABLE_n */ - PAD_CFG_NF(GPD11, NONE, DEEP, NF1), - - /* ------- GPIO Group GPP_K ------- */ - /* GPP_K0 - PERST_PCH_SLOTS_n : configured at runtime */ - /* GPP_K1 - PERST_CPU_SLOTS_n : configured at runtime */ - /* GPP_K2 - PERST_CNVI_SLOTS_n : configured at runtime */ - /* GPP_K3 - DP1_PWR_EN : configured at runtime */ - /* GPP_K4 - DP2_PWR_EN : configured at runtime */ - /* GPP_K5 - DP3_PWR_EN : configured at runtime */ - - PAD_NC(GPP_K6, NONE), - - /* GPP_K7 - EN_3V3_KEYM_PCH : configured at runtime */ - - PAD_NC(GPP_K8, NONE), - PAD_NC(GPP_K9, NONE), - PAD_NC(GPP_K10, NONE), - PAD_NC(GPP_K11, NONE), - - /* K12 - K16 in early GPIO config */ - - PAD_NC(GPP_K17, NONE), - - /* GPP_K18/!NMI - NC */ - PAD_NC(GPP_K18, NONE), - /* GPP_K19/!SMI - NC */ - PAD_NC(GPP_K19, NONE), - - /* GPP_K20 - CPU_CATERR_PCH_n */ - PAD_CFG_GPI(GPP_K20, NONE, DEEP), - /* GPP_K21 - TPM_INT_n */ - PAD_CFG_GPI_INT(GPP_K21, NONE, DEEP, OFF), /* Trigger? */ - /* GPP_K22 - NC */ - PAD_NC(GPP_K22, NONE), - /* GPP_K23 - NC */ - PAD_NC(GPP_K23, NONE), - - /* ------- GPIO Group GPP_H ------- */ - - /* SRCCLKREQ6# - SRCCLKREQ10# not used as CLKREQ, external 10K pullup */ - PAD_CFG_GPI(GPP_H0, NONE, DEEP), /* PCIE_SLOT1_PRSNT_PCH_n */ - PAD_CFG_GPI(GPP_H1, NONE, DEEP), /* PCIE_SLOT2_PRSNT_PCH_n */ - PAD_CFG_GPI(GPP_H2, NONE, DEEP), /* PCIE_SLOT3_PRSNT_PCH_n */ - PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* PCIE_SLOT4_PRSNT_PCH_n */ - PAD_CFG_GPI(GPP_H4, NONE, DEEP), /* PCIE_SLOT6_PRSNT_PCH_n */ - - PAD_CFG_GPI(GPP_H4, NONE, DEEP), /* PCIE_SLOT6_PRSNT_PCH_n */ - - /* GPP_H5 - PCH_HBLED_n configured in early init */ - - /* SRCCLKREQ13# - SRCCLKREQ15# */ - PAD_NC(GPP_H7, NONE), - PAD_NC(GPP_H8, NONE), - PAD_NC(GPP_H9, NONE), - - /* SML2 - Used by CSME */ - PAD_NC(GPP_H10, NONE), - PAD_NC(GPP_H11, NONE), - PAD_NC(GPP_H12, NONE), - - /* SML3 - Used by CSME */ - PAD_NC(GPP_H13, NONE), - PAD_NC(GPP_H14, NONE), - PAD_NC(GPP_H15, NONE), - - /* SML4 - Used by CSME */ - PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), /* PCIE_SMB_CLK */ - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* PCIE_SMB_DATA */ - PAD_NC(GPP_H18, NONE), - - /* ISH I2C0 */ - PAD_NC(GPP_H19, NONE), - PAD_NC(GPP_H20, NONE), - - /* ISH I2C1 */ - PAD_NC(GPP_H21, NONE), - PAD_NC(GPP_H22, NONE), - - PAD_NC(GPP_H23, NONE), - - /* ------- GPIO Group GPP_E ------- */ - /* GPP_E0 - NC */ - PAD_NC(GPP_E0, NONE), - /* GPP_E1 - M2_SATA_PCIE_SEL */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* GPP_E2 - NC */ - PAD_NC(GPP_E2, NONE), - /* GPP_E3 - NC */ - PAD_NC(GPP_E3, NONE), - /* GPP_E4 - NC */ - PAD_NC(GPP_E4, NONE), - - /* GPP_E5 - PCH_M2_SATA_DEVSLP1 */ - PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), - /* GPP_E6 - NC */ - PAD_NC(GPP_E6, NONE), - /* GPP_E8 - SATALED# */ - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), - - /* GPP_E9 - USB31_RP1_OC_N */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* GPP_E10 - USB31_RP2_OC_N */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - /* GPP_E11 - USB31_FP_OC_N */ - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), - /* GPP_E12 - USB2_FP1_OC_N */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), - - /* ------- GPIO Group GPP_F ------- */ - /* SATAGP3-7 */ - PAD_NC(GPP_F0, NONE), - PAD_NC(GPP_F1, NONE), - PAD_NC(GPP_F2, NONE), - PAD_NC(GPP_F3, NONE), - PAD_NC(GPP_F4, NONE), - - /* SATA DEVSLP3-7 */ - PAD_NC(GPP_F5, NONE), - PAD_NC(GPP_F6, NONE), - PAD_NC(GPP_F7, NONE), - PAD_NC(GPP_F8, NONE), - PAD_NC(GPP_F9, NONE), - - /* SGPIO has external 2K pullups */ - /* GPP_F10 - SATA_SCLOCK */ - PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), - /* GPP_F11 - SATA_SLOAD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* GPP_F12 - SATA_SDATAOUT1 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* GPP_F13 - SATA_BMC_SDATAOUT0 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - - /* GPP_F14 - PS_ON_PCH_n */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF2), - /* GPP_F15 - USB2_FP2_OC_N */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - - /* GPP_F16 - NC/PU */ - PAD_NC(GPP_F16, NONE), - /* GPP_F17 - GPIO */ - PAD_NC(GPP_F17, NONE), - /* GPP_F18 - GPIO */ - PAD_NC(GPP_F18, NONE), - /* GPP_F19 - GPIO */ - PAD_NC(GPP_F19, NONE), - /* GPP_F20 - GPIO */ - PAD_NC(GPP_F20, NONE), - /* GPP_F21 - GPIO */ - PAD_NC(GPP_F21, NONE), - /* GPP_F22 - GPIO */ - PAD_NC(GPP_F22, NONE), - /* GPP_F23 - NC */ - PAD_NC(GPP_F23, NONE), - /* GPP_J0 - CNV_GNSS_PA_BLANKING */ - PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), - /* GPP_J1 - NC */ - PAD_NC(GPP_J1, NONE), - /* GPP_J2 - NC */ - PAD_NC(GPP_J2, NONE), - /* GPP_J3 - NC */ - PAD_NC(GPP_J3, NONE), - - /* CNVi */ - /* GPP_J4 - CNV_BRI_DT*/ - PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), - /* GPP_J5 - CNV_BRI_RSP */ - PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), - /* GPP_J6 - CNV_RGI_DT */ - PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), - /* GPP_J7 - CNV_RGI_RSP */ - PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), - /* GPP_J8 - CNV_MFUART2_RXD */ - PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), - /* GPP_J9 - CNV_MFUART2_TXD */ - PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), - - PAD_NC(GPP_J10, NONE), - PAD_NC(GPP_J11, NONE), - - /* Display Port */ - PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* DP1_HPD */ - PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), /* DP2_HPD */ - PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), /* DP3_HPD */ - PAD_NC(GPP_I3, NONE), - PAD_NC(GPP_I4, NONE), - - PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), /* DP1_DDC_SCL */ - PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), /* DP1_DDC_SDA */ - - PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* DP2_DDC_SCL */ - PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* DP2_DDC_SDA */ - - PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* DP3_DDC_SCL */ - PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* DP3_DDC_SDA */ - - PAD_NC(GPP_I11, NONE), - PAD_NC(GPP_I12, NONE), - PAD_NC(GPP_I13, NONE), - PAD_NC(GPP_I14, NONE), - -}; - -/* Early pad configuration in bootblock. */ -const struct pad_config early_gpio_table[] = { - /* Get PCIe out of reset */ - PAD_CFG_GPO(GPP_K0, 1, DEEP), /* PERST_PCH_SLOTS_n */ - PAD_CFG_GPO(GPP_K1, 1, DEEP), /* PERST_CPU_SLOTS_n */ - PAD_CFG_GPO(GPP_K2, 1, DEEP), /* PERST_CNVI_SLOTS_n */ - - /* SMB */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_SMB_CLK */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_SMB_DATA */ - PAD_NC(GPP_C2, NONE), - - /* BMC HSI */ - PAD_CFG_GPI(GPP_K12, NONE, DEEP), /* PCH_IO_2 */ - PAD_CFG_GPI(GPP_K13, NONE, DEEP), /* PCH_IO_3 */ - PAD_CFG_GPI(GPP_K14, NONE, DEEP), /* PCH_IO_1 */ - PAD_NC(GPP_K15, NONE), - PAD_CFG_GPI(GPP_K16, NONE, DEEP), /* PCH_IO_0 */ - - /* LED */ - PAD_CFG_GPO(GPP_H5, 0, DEEP), /* PCH_HBLED_n */ - - /* UART0 */ - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0_TXD */ - - /* UART1 */ - PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1_RXD */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_TXD */ - - /* UART2 */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ -}; - -void program_gpio_pads(void) -{ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -} - -void program_early_gpio_pads(void) -{ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/hda_verb.c b/src/mainboard/prodrive/hermes/variants/baseboard/hda_verb.c deleted file mode 100644 index d20f35d508..0000000000 --- a/src/mainboard/prodrive/hermes/variants/baseboard/hda_verb.c +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -const u32 cim_verb_data[] = { - 0x10ec0888, /* Codec Vendor / Device ID: Realtek ALC888 */ - 0x10ec0888, /* Subsystem ID */ - 15, /* Number of 4 dword sets */ - AZALIA_SUBVENDOR(0, 0x1d336700), - - /* Pin widgets */ - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), /* SPDIF-OUT2 - disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), /* digital MIC - disabled */ - AZALIA_PIN_CFG(0, 0x14, 0x01014430), /* PORT D - rear line out */ - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), /* PORT G - disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), /* PORT H - disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), /* PORT B - rear mic in */ - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), /* CD audio - disabled */ - AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), /* BEEPIN */ - AZALIA_PIN_CFG(0, 0x1e, 0x01452160), /* SPDIF-OUT */ - AZALIA_PIN_CFG(0, 0x1f, 0x01C52170), /* SPDIF-IN */ - - /* Config for R02 and older */ - AZALIA_PIN_CFG(0, 0x19, 0x02214c40), /* port F - front hp out */ - AZALIA_PIN_CFG(0, 0x1a, 0x901001f0), /* port C - internal speaker */ - AZALIA_PIN_CFG(0, 0x1b, 0x01813c10), /* port E - rear line in/mic - Blue */ - AZALIA_PIN_CFG(0, 0x15, 0x02a19c20), /* port A - audio hdr input */ - - /* - * VerbTable: CFL Display Audio Codec - * Revision ID = 0xFF - * Codec Vendor: 0x8086280B - */ - 0x8086280B, - 0xFFFFFFFF, - 5, /* Number of 4 dword sets */ - - AZALIA_SUBVENDOR(2, 0x80860101), - - /* - * Display Audio Verb Table - * For GEN9, the Vendor Node ID is 08h - * Port to be exposed to the inbox driver in the vanilla mode - * PORT C - BIT[7:6] = 01b - */ - 0x20878101, - - /* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */ - AZALIA_PIN_CFG(2, 0x05, 0x18560010), - /* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */ - AZALIA_PIN_CFG(2, 0x06, 0x18560020), - /* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */ - AZALIA_PIN_CFG(2, 0x07, 0x18560030), - /* Disable the third converter and third Pin (NID 08h) */ - 0x20878100, - - /* Dummy entries */ - 0x20878100, - 0x20878100, -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h deleted file mode 100644 index 0d4e9d8e31..0000000000 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h +++ /dev/null @@ -1,121 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include - -union eeprom_dimm_layout { - struct __packed { - char name[50]; - char manufacturer[50]; - uint8_t ranks; - uint8_t controller_id; - uint8_t data_width_bits; - uint8_t bus_width_bits; - uint32_t capacity_mib; - uint32_t max_tdp_milliwatts; - }; - uint8_t raw[0x80]; -}; - -_Static_assert(sizeof(union eeprom_dimm_layout) == 0x80, - "union eeprom_dimm_layout has invalid size!"); - -struct __packed eeprom_board_layout { - uint32_t signature; - union { - struct __packed { - char cpu_name[50]; - uint8_t cpu_count; - uint32_t cpu_max_non_turbo_frequency; - char pch_name[50]; - union eeprom_dimm_layout dimm[4]; - }; - uint8_t raw_layout[617]; - }; -}; - -_Static_assert(sizeof(struct eeprom_board_layout) == (617 + sizeof(uint32_t)), - "struct eeprom_board_layout has invalid size!"); - -struct __packed eeprom_board_settings { - uint32_t signature; - union { - struct __packed { - uint8_t secureboot; - uint8_t primary_video; - uint8_t deep_sx_enabled; - uint8_t wake_on_usb; - uint8_t usb_powered_in_s5; - uint8_t power_state_after_g3; - uint8_t blue_rear_vref; - uint8_t front_panel_audio; - uint8_t pxe_boot_capability; - }; - uint8_t raw_settings[9]; - }; -}; - -_Static_assert(sizeof(struct eeprom_board_settings) == (9 + sizeof(uint32_t)), - "struct eeprom_board_settings has invalid size!"); - -struct __packed eeprom_bmc_settings { - uint8_t pcie_mux; - uint8_t hsi; -}; - -#define HERMES_SERIAL_NUMBER_LENGTH 32 - -/* The EEPROM on address 0x57 has the following vendor defined layout: */ -struct __packed eeprom_layout { - union { - uint8_t RawFSPMUPD[0x600]; - FSPM_UPD mupd; - }; - union { - uint8_t RawFSPSUPD[0xC00]; - FSPS_UPD supd; - }; - union { - uint8_t RawBoardLayout[0x400]; - struct eeprom_board_layout BoardLayout; - }; - char system_serial_number[HERMES_SERIAL_NUMBER_LENGTH]; - char board_serial_number[HERMES_SERIAL_NUMBER_LENGTH]; - uint8_t BootOrder[0x8c0]; - union { - uint8_t RawBoardSetting[0xF8]; - struct eeprom_board_settings BoardSettings; - }; - union { - uint8_t RawBMCSetting[0x8]; - struct eeprom_bmc_settings BMCSettings; - }; -}; - -_Static_assert(sizeof(FSPM_UPD) <= 0x600, "FSPM_UPD too big"); -_Static_assert(sizeof(FSPS_UPD) <= 0xC00, "FSPS_UPD too big"); -_Static_assert(sizeof(struct eeprom_layout) == 0x2000, "EEPROM layout size mismatch"); - -bool eeprom_read_buffer(void *blob, size_t read_offset, size_t size); -int check_signature(const size_t offset, const uint64_t signature); -struct eeprom_board_settings *get_board_settings(void); -struct eeprom_bmc_settings *get_bmc_settings(void); -uint8_t get_bmc_hsi(void); -void report_eeprom_error(const size_t off); -bool write_board_settings(const struct eeprom_board_layout *new_layout); - -#define READ_EEPROM(section_type, section_name, dest, opt_name) \ - do { \ - typeof(dest->opt_name) __tmp; \ - size_t __off = offsetof(struct eeprom_layout, section_name); \ - bool ret = eeprom_read_buffer(&__tmp, \ - __off + offsetof(section_type, opt_name), \ - sizeof(__tmp)); \ - if (ret) { \ - report_eeprom_error(__off + offsetof(section_type, opt_name)); \ - } else { \ - dest->opt_name = __tmp; \ - } \ - } while (0) - -#define READ_EEPROM_FSP_M(dest, opt_name) READ_EEPROM(FSPM_UPD, RawFSPMUPD, dest, opt_name) -#define READ_EEPROM_FSP_S(dest, opt_name) READ_EEPROM(FSPS_UPD, RawFSPSUPD, dest, opt_name) diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h deleted file mode 100644 index 8fce3c8b39..0000000000 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef PCH_GPIO_H -#define PCH_GPIO_H - -void program_gpio_pads(void); -void program_early_gpio_pads(void); - -#endif /* PCH_GPIO_H */ diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/variants.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/variants.h deleted file mode 100644 index 54a116143f..0000000000 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/variants.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -/* Return memory configuration structure. */ -const struct cnl_mb_cfg *variant_memcfg_config(void); - -void mainboard_r0x_configure_alc888(u8 *base, u32 viddid); diff --git a/src/mainboard/prodrive/hermes/variants/r04/hda_verb.c b/src/mainboard/prodrive/hermes/variants/r04/hda_verb.c deleted file mode 100644 index b4a337085b..0000000000 --- a/src/mainboard/prodrive/hermes/variants/r04/hda_verb.c +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -#include "variant/variants.h" -#include "eeprom.h" - -static const u32 r04_verb_data[] = { - AZALIA_PIN_CFG(0, 0x19, 0x02a19c20), /* PORT F - front mic in */ - AZALIA_PIN_CFG(0, 0x1a, 0x01813c51), /* PORT C - rear line in (mic support) */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), /* PORT E - disabled */ - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), /* PORT A - disabled */ -}; - -static u32 get_port_c_vref_cfg(uint8_t blue_rear_vref) -{ - switch (blue_rear_vref) { - default: - case 0: - return 0x02040000; - case 1: - return 0x02041000; - case 2: - return 0x02044000; - case 3: - return 0x02045000; - case 4: - return 0x02046000; - } -} - -static u32 get_front_panel_cfg(uint8_t front_panel_audio) -{ - switch (front_panel_audio) { - default: - case 0: - return AZALIA_PIN_CFG_NC(0); - case 1: - return 0x022a4c40; - case 2: - return AZALIA_PIN_DESC( - INTEGRATED, - INTERNAL, - NA, - SPEAKER, - TYPE_UNKNOWN, - COLOR_UNKNOWN, - false, - 0xf, - 0); - } -} - -void mainboard_r0x_configure_alc888(u8 *base, u32 viddid) -{ - /* Overwrite settings made by baseboard */ - azalia_program_verb_table(base, r04_verb_data, ARRAY_SIZE(r04_verb_data)); - - const struct eeprom_board_settings *const board_cfg = get_board_settings(); - - if (!board_cfg) - return; - - const u32 front_panel_cfg = get_front_panel_cfg(board_cfg->front_panel_audio); - - const u32 verbs[] = { - AZALIA_PIN_CFG(0, 0x1b, front_panel_cfg), - 0x0205000d, /* Pin 37 vrefo hidden register - used as port C vref */ - get_port_c_vref_cfg(board_cfg->blue_rear_vref), - }; - azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs)); -} -- cgit v1.2.3