From e69a9c75816dd3cd6a9af50a09eb090ea00cfed4 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 20 Aug 2017 14:48:57 -0500 Subject: google/cyan: convert to variant configuration Setup cyan to be the baseboard for other Google Braswell boards, to be added in subsequent commits: - Keep code common to all Google Braswell boards in the baseboard, and separate out the board-specific bits into the new cyan variant. - Define the I2C ACPI devices such that they can be easily reused for other variants. - Switch the trackpad/touchscreen interrupts from edge to level, for better performance/compatibility, as was done with all previous Google boards. - Add code to the baseboard to allow optional variant-specific parameters to be used for both memory and silicon init. - Remove superfluous includes, replace some hardcoded values with variables, and correct typos/formatting errors. Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/21126 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/cyan/Kconfig | 23 +- src/mainboard/google/cyan/Kconfig.name | 1 + src/mainboard/google/cyan/Makefile.inc | 15 +- src/mainboard/google/cyan/acpi/codec_maxim.asl | 117 ++++++++++ src/mainboard/google/cyan/acpi/dptf.asl | 63 +---- src/mainboard/google/cyan/acpi/ec.asl | 2 +- src/mainboard/google/cyan/acpi/mainboard.asl | 188 +-------------- src/mainboard/google/cyan/acpi/superio.asl | 2 +- .../google/cyan/acpi/touchscreen_elan.asl | 61 +++++ src/mainboard/google/cyan/acpi/trackpad_elan.asl | 53 +++++ src/mainboard/google/cyan/acpi_tables.c | 10 - src/mainboard/google/cyan/board_info.txt | 2 +- src/mainboard/google/cyan/boardid.c | 4 +- src/mainboard/google/cyan/devicetree.cb | 143 ------------ src/mainboard/google/cyan/gpio.c | 260 --------------------- src/mainboard/google/cyan/mainboard.c | 2 - src/mainboard/google/cyan/onboard.h | 75 ------ src/mainboard/google/cyan/ramstage.c | 3 +- src/mainboard/google/cyan/romstage.c | 7 +- src/mainboard/google/cyan/smihandler.c | 2 +- src/mainboard/google/cyan/spd/Makefile.inc | 42 ---- src/mainboard/google/cyan/spd/spd.c | 67 ++---- src/mainboard/google/cyan/spd/spd_util.h | 22 ++ .../google/cyan/variants/cyan/Makefile.inc | 44 ++++ .../google/cyan/variants/cyan/board_info.txt | 6 + .../google/cyan/variants/cyan/devicetree.cb | 143 ++++++++++++ src/mainboard/google/cyan/variants/cyan/gpio.c | 260 +++++++++++++++++++++ .../variants/cyan/include/variant/acpi/dptf.asl | 73 ++++++ .../cyan/include/variant/acpi/mainboard.asl | 24 ++ .../cyan/variants/cyan/include/variant/onboard.h | 75 ++++++ src/mainboard/google/cyan/variants/cyan/spd_util.c | 68 ++++++ 31 files changed, 1003 insertions(+), 854 deletions(-) create mode 100644 src/mainboard/google/cyan/acpi/codec_maxim.asl create mode 100644 src/mainboard/google/cyan/acpi/touchscreen_elan.asl create mode 100644 src/mainboard/google/cyan/acpi/trackpad_elan.asl delete mode 100644 src/mainboard/google/cyan/devicetree.cb delete mode 100644 src/mainboard/google/cyan/gpio.c delete mode 100644 src/mainboard/google/cyan/onboard.h delete mode 100644 src/mainboard/google/cyan/spd/Makefile.inc create mode 100644 src/mainboard/google/cyan/spd/spd_util.h create mode 100644 src/mainboard/google/cyan/variants/cyan/Makefile.inc create mode 100644 src/mainboard/google/cyan/variants/cyan/board_info.txt create mode 100644 src/mainboard/google/cyan/variants/cyan/devicetree.cb create mode 100644 src/mainboard/google/cyan/variants/cyan/gpio.c create mode 100644 src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl create mode 100644 src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h create mode 100644 src/mainboard/google/cyan/variants/cyan/spd_util.c (limited to 'src') diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 6cfec3a577..f4f98309d6 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -1,7 +1,5 @@ -if BOARD_GOOGLE_CYAN - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_GOOGLE_BASEBOARD_CYAN + def_bool n select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC @@ -14,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_BRASWELL select HAVE_ACPI_RESUME +if BOARD_GOOGLE_BASEBOARD_CYAN + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH @@ -33,14 +33,22 @@ config MAINBOARD_DIR string default google/cyan +config VARIANT_DIR + string + default "cyan" if BOARD_GOOGLE_CYAN + config MAINBOARD_PART_NUMBER string - default "Cyan" + default "Cyan" if BOARD_GOOGLE_CYAN config MAINBOARD_VENDOR string default "Google" +config DEVICETREE + string + default "variants/cyan/devicetree.cb" if BOARD_GOOGLE_CYAN + config VGA_BIOS_FILE string depends on VGA_BIOS @@ -61,5 +69,6 @@ config VGA_BIOS_ID config GBB_HWID string depends on CHROMEOS - default "CYAN TEST A-A 1829" -endif # BOARD_GOOGLE_CYAN + default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN + +endif # BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name index a4562d3a39..91e10c9613 100644 --- a/src/mainboard/google/cyan/Kconfig.name +++ b/src/mainboard/google/cyan/Kconfig.name @@ -1,2 +1,3 @@ config BOARD_GOOGLE_CYAN bool "Cyan" + select BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 43e3c9591d..01c2a91099 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -14,17 +14,18 @@ ## GNU General Public License for more details. ## -subdirs-y += spd - -romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c +romstage-y += spd/spd.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-y += boardid.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c -ramstage-y += boardid.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl new file mode 100644 index 0000000000..9abc91e3fa --- /dev/null +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C2) +{ + /* Maxim Audio Codec */ + Device (MAXM) /* Audio Codec driver I2C */ + { + Name (_ADR, 0) + Name (_HID, AUDIO_CODEC_HID) + Name (_CID, AUDIO_CODEC_CID) + Name (_DDN, AUDIO_CODEC_DDN) + Name (_UID, 1) + + /* Add DT style bindings with _DSD */ + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + /* set maxim micbias to 2.8v */ + Package () { "maxim,micbias", 3 }, + } + }) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } + } ) + Return (SBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } + Device (TISW) /* TI Switch driver I2C */ + { + Name (_ADR, 0) + Name (_HID, TI_SWITCH_HID) + Name (_CID, TI_SWITCH_CID) + Name (_DDN, TI_SWITCH_DDN) + Name (_UID, 1) + + /* Add DT style bindings with _DSD */ + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + /* set ti micbias to 2.8v */ + Package () { "ti,micbias", 7 }, + } + }) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX } + + } ) + Return (SBUF) + } + + Method (_STA) + { + Return (0xF) + } + } +} + + +Scope (\_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } + }) +} diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index 95b6951279..d0eaadd94f 100644 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,63 +14,8 @@ * GNU General Public License for more details. */ -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 49 -#define DPTF_TSR0_CRITICAL 75 +/* Include Variant DPTF */ +#include -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 65 -#define DPTF_TSR1_CRITICAL 85 - -#define DPTF_TSR2_SENSOR_ID 2 -#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 49 -#define DPTF_TSR2_CRITICAL 75 - -#define DPTF_ENABLE_CHARGER - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x400, "mA", 0 }, /* 1.0A (MAX) */ - Package () { 0, 0, 0, 0, 12, 0x300, "mA", 0 }, /* 0.77A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 4, 0x100, "mA", 0 }, /* 0.25A */ - Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ -}) - -/* Mainboard specific _PDL is 1GHz */ -Name (MPDL, 8) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 2000, /* PowerLimitMinimum */ - 6200, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 8000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) - -/* Include DPTF */ +/* Include SoC DPTF */ #include diff --git a/src/mainboard/google/cyan/acpi/ec.asl b/src/mainboard/google/cyan/acpi/ec.asl index ab89841f3d..271fd0a867 100644 --- a/src/mainboard/google/cyan/acpi/ec.asl +++ b/src/mainboard/google/cyan/acpi/ec.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Google Inc. - * Copyright (C) 2105 Intel Corp. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl index 7a4b0ea355..3228a31bfa 100644 --- a/src/mainboard/google/cyan/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ -#include +#include Scope (\_SB) { @@ -26,189 +26,6 @@ Scope (\_SB) } } -Scope (\_SB.PCI0.I2C1) -{ - Device (ETSA) - { - Name (_HID, "ELAN0001") - Name (_DDN, "Elan Touchscreen ") - Name (_UID, 5) - Name (ISTP, 0) /* TouchScreen */ - - Method(_CRS, 0x0, NotSerialized) - { - Name(BUF0,ResourceTemplate () - { - I2CSerialBus( - 0x10, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C1", /* ResourceSource */ - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TOUCH_IRQ - } - - } ) - Return (BUF0) - } - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } -} - -Scope (\_SB.PCI0.I2C2) -{ - /* Maxim Audio Codec */ - Device (MAXM) /* Audio Codec driver I2C */ - { - Name (_ADR, 0) - Name (_HID, AUDIO_CODEC_HID) - Name (_CID, AUDIO_CODEC_CID) - Name (_DDN, AUDIO_CODEC_DDN) - Name (_UID, 1) - - /* Add DT style bindings with _DSD */ - Name (_DSD, Package () { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - /* set maxim micbias to 2.8v */ - Package () { "maxim,micbias", 3 }, - } - }) - - Method(_CRS, 0x0, NotSerialized) - { - Name(SBUF,ResourceTemplate () - { - I2CSerialBus( - AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ - ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ - 400000, /* ConnectionSpeed: in Hz */ - AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ - "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ - ) - - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } - } ) - Return (SBUF) - } - - Method (_STA) - { - If (LEqual (\S2EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } - Device (TISW) /* TI Switch driver I2C */ - { - Name (_ADR, 0) - Name (_HID, TI_SWITCH_HID) - Name (_CID, TI_SWITCH_CID) - Name (_DDN, TI_SWITCH_DDN) - Name (_UID, 1) - - /* Add DT style bindings with _DSD */ - Name (_DSD, Package () { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - /* set ti micbias to 2.8v */ - Package () { "ti,micbias", 7 }, - } - }) - - Method(_CRS, 0x0, NotSerialized) - { - Name(SBUF,ResourceTemplate () - { - I2CSerialBus( - TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */ - ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ - 400000, /* ConnectionSpeed: in Hz */ - AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ - "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ - ) - - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX } - - } ) - Return (SBUF) - } - - Method (_STA) - { - Return (0xF) - } - } -} - -Scope (\_SB.PCI0.I2C6) -{ - Device (ETPA) - { - Name (_HID, "ELAN0000") - Name (_DDN, "Elan Touchpad") - Name (_UID, 3) - Name (ISTP, 1) /* Touchpad */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x15, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C6", /* ResourceSource */ - ) - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } - }) - - Method (_STA) - { - If (LEqual (\S6EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } -} - -Scope (\_SB.PCI0.LPEA) -{ - Name (GBUF, ResourceTemplate () - { - /* Jack Detect (index 0) */ - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } - }) -} - Scope (\_SB.GPNC) { Method (_AEI, 0, NotSerialized) // _AEI: ACPI Event Interrupts @@ -225,3 +42,6 @@ Scope (\_SB.GPNC) { } } + +/* Variant-specific I2C devices */ +#include diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl index f2a7fc0296..ca973d0fab 100644 --- a/src/mainboard/google/cyan/acpi/superio.asl +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -16,7 +16,7 @@ /* mainboard configuration */ #include -#include +#include #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ diff --git a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl new file mode 100644 index 0000000000..7100120585 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C1) +{ + Device (ETSA) + { + Name (_HID, "ELAN0001") + Name (_DDN, "Elan Touchscreen ") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Method(_CRS, 0x0, NotSerialized) + { + Name(BUF0,ResourceTemplate () + { + I2CSerialBus( + 0x10, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.PCI0.I2C1", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TOUCH_IRQ + } + + } ) + Return (BUF0) + } + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/cyan/acpi/trackpad_elan.asl b/src/mainboard/google/cyan/acpi/trackpad_elan.asl new file mode 100644 index 0000000000..f89e1bc23f --- /dev/null +++ b/src/mainboard/google/cyan/acpi/trackpad_elan.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C6) +{ + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x15, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.PCI0.I2C6", /* ResourceSource */ + ) + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c index d4271e5e99..a0da53f52c 100644 --- a/src/mainboard/google/cyan/acpi_tables.c +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -15,19 +15,9 @@ */ #include -#include #include -#include -#include -#include -#include -#include -#include #include -#include #include -#include -#include void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/google/cyan/board_info.txt b/src/mainboard/google/cyan/board_info.txt index 8815b3674e..98f3d76533 100644 --- a/src/mainboard/google/cyan/board_info.txt +++ b/src/mainboard/google/cyan/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Google -Board name: Cyan Braswell reference board +Board name: Cyan Braswell baseboard Category: laptop ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/google/cyan/boardid.c b/src/mainboard/google/cyan/boardid.c index 15d26dc53f..5364bb9a0b 100644 --- a/src/mainboard/google/cyan/boardid.c +++ b/src/mainboard/google/cyan/boardid.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright(C) 2013 Google Inc. + * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify @@ -16,7 +16,7 @@ #include #include -#include "ec/google/chromeec/ec.h" +#include uint8_t board_id(void) { diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb deleted file mode 100644 index 0454650c68..0000000000 --- a/src/mainboard/google/cyan/devicetree.cb +++ /dev/null @@ -1,143 +0,0 @@ -chip soc/intel/braswell - - ############################################################ - # Set the parameters for MemoryInit - ############################################################ - - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" - register "PcdMrcInitSpdAddr1" = "0xa0" - register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" - register "PcdDvfsEnable" = "1" - register "PcdCaMirrorEn" = "0" - - ############################################################ - # Set the parameters for SiliconInit - ############################################################ - - register "PcdSdcardMode" = "PCH_ACPI_MODE" - register "PcdEnableHsuart0" = "0" - register "PcdEnableHsuart1" = "1" - register "PcdEnableAzalia" = "1" - register "PcdEnableXhci" = "1" - register "PcdEnableLpe" = "1" - register "PcdEnableDma0" = "1" - register "PcdEnableDma1" = "1" - register "PcdEnableI2C0" = "1" - register "PcdEnableI2C1" = "1" - register "PcdEnableI2C2" = "0" - register "PcdEnableI2C3" = "0" - register "PcdEnableI2C4" = "0" - register "PcdEnableI2C5" = "1" - register "PcdEnableI2C6" = "0" - register "PunitPwrConfigDisable" = "0" # Enable SVID - register "ChvSvidConfig" = "SVID_CONFIG1" - register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" - register "PcdEnableSata" = "0" # Disable SATA - register "Usb2Port0PerPortPeTxiSet" = "7" - register "Usb2Port0PerPortTxiSet" = "5" - register "Usb2Port0IUsbTxEmphasisEn" = "2" - register "Usb2Port0PerPortTxPeHalf" = "1" - register "Usb2Port1PerPortPeTxiSet" = "7" - register "Usb2Port1PerPortTxiSet" = "3" - register "Usb2Port1IUsbTxEmphasisEn" = "2" - register "Usb2Port1PerPortTxPeHalf" = "1" - register "Usb2Port2PerPortPeTxiSet" = "7" - register "Usb2Port2PerPortTxiSet" = "3" - register "Usb2Port2IUsbTxEmphasisEn" = "2" - register "Usb2Port2PerPortTxPeHalf" = "1" - register "Usb2Port3PerPortPeTxiSet" = "7" - register "Usb2Port3PerPortTxiSet" = "3" - register "Usb2Port3IUsbTxEmphasisEn" = "2" - register "Usb2Port3PerPortTxPeHalf" = "1" - register "Usb2Port4PerPortPeTxiSet" = "7" - register "Usb2Port4PerPortTxiSet" = "3" - register "Usb2Port4IUsbTxEmphasisEn" = "2" - register "Usb2Port4PerPortTxPeHalf" = "1" - register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" - register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" - register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" - register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM - register "PMIC_I2CBus" = "0" - register "ISPEnable" = "0" # Disable IUNIT - register "ISPPciDevConfig" = "3" - register "PcdSdDetectChk" = "0" # Disable SD card detect - - # LPE audio codec settings - register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - - # Enable devices in ACPI mode - register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" - register "lpe_acpi_mode" = "1" - - # Disable SLP_X stretching after SUS power well fail. - register "disable_slp_x_stretch_sus_fail" = "1" - - # Allow PCIe devices to wake system from suspend - register "pcie_wake_enable" = "1" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - # EDS Table 24-4, Figure 24-5 - device pci 00.0 on end # 8086 2280 - SoC transaction router - device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? - device pci 10.0 on end # 8086 2294 - MMC Port - device pci 11.0 off end # 8086 0F15 - SDIO Port - device pci 12.0 on end # 8086 0F16 - SD Port - device pci 13.0 off end # 8086 22a3 - Sata controller - device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time - device pci 15.0 on end # 8086 22a8 - LP Engine Audio - device pci 16.0 off end # 8086 22b7 - USB device - device pci 18.0 on end # 8086 22c0 - SIO - DMA - device pci 18.1 on end # 8086 22c1 - I2C Port 1 - device pci 18.2 on end # 8086 22c2 - I2C Port 2 - device pci 18.3 off end # 8086 22c3 - I2C Port 3 - device pci 18.4 off end # 8086 22c4 - I2C Port 4 - device pci 18.5 off end # 8086 22c5 - I2C Port 5 - device pci 18.6 on end # 8086 22c6 - I2C Port 6 - device pci 18.7 off end # 8086 22c7 - I2C Port 7 - device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 2284 - HD Audio - device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1 - device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3 - device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 - device pci 1e.0 on end # 8086 2286 - SIO - DMA - device pci 1e.1 off end # 8086 0F08 - PWM 1 - device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 228a - HSUART 1 - device pci 1e.4 off end # 8086 228c - HSUART 2 - device pci 1e.5 on end # 8086 228e - SPI 1 - device pci 1e.6 off end # 8086 2290 - SPI 2 - device pci 1e.7 off end # 8086 22ac - SPI 3 - device pci 1f.0 on # 8086 229c - LPC bridge - chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Bridge - device pci 1f.3 off end # 8086 0F12 - SMBus 0 - end -end diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c deleted file mode 100644 index f35b07e518..0000000000 --- a/src/mainboard/google/cyan/gpio.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright(C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" -#include -#include - -/* South East Community */ -static const struct soc_gpio_map gpse_gpio_map[] = { - Native_M1,/* MF_PLT_CLK0 */ - GPIO_NC, /* 01 PWM1 */ - GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ - GPIO_NC, /* 03 MF_PLT_CLK4 */ - GPIO_NC, /* 04 MF_PLT_CLK3 */ - GPIO_NC, /* PWM0 05 */ - GPIO_NC, /* 06 MF_PLT_CLK5 */ - GPIO_NC, /* 07 MF_PLT_CLK2 */ - GPIO_NC, /* 15 SDMMC2_D3_CD_B */ - Native_M1, /* 16 SDMMC1_CLK */ - NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ - GPIO_NC, /* 18 SDMMC2_D1 */ - GPIO_NC, /* 19 SDMMC2_CLK */ - NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ - GPIO_NC, /* 21 SDMMC2_D2 */ - GPIO_NC, /* 22 SDMMC2_CMD */ - NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ - NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ - GPIO_NC, /* 25 SDMMC2_D0 */ - NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ - NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ - Native_M1, /* 31 SDMMC3_CLK */ - NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ - NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ - NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ - NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ - NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ - Native_M1, /* 46 LPC_CLKRUNB */ - NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ - Native_M1, /* 48 LPC_FRAMEB */ - Native_M1, /* 49 MF_LPC_CLKOUT1 */ - NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ - Native_M1, /* 51 MF_LPC_CLKOUT0 */ - NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ - Native_M1,/* SPI1_MISO */ - Native_M1, /* 61 SPI1_CS0_B */ - Native_M1, /* SPI1_CLK */ - NATIVE_PU20K(1), /* 63 MMC1_D6 */ - Native_M1, /* 62 SPI1_MOSI */ - NATIVE_PU20K(1), /* 65 MMC1_D5 */ - GPIO_NC, /* SPI1_CS1_B 66 */ - NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ - NATIVE_PU20K(1), /* 68 MMC1_D7 */ - GPIO_NC, /* 69 MMC1_RCLK */ - Native_M1, /* 75 GPO USB_OC1_B */ - Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), - /* GPIO_ALERT 77 */ - Native_M1, /* 78 SDMMC3_PWR_EN_B */ - GPIO_NC, /* 79 GPI ILB_SERIRQ */ - Native_M1, /* 80 USB_OC0_B */ - NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ - GPIO_NC, /* 82 spkr asummed gpio number */ - Native_M1, /* 83 SUSPWRDNACK */ - SPARE_PIN,/* 84 spare pin */ - Native_M1, /* 85 SDMMC3_1P8_EN */ - GPIO_END -}; - - -/* South West Community */ -static const struct soc_gpio_map gpsw_gpio_map[] = { - GPIO_NC, /* 00 FST_SPI_D2 */ - Native_M1, /* 01 FST_SPI_D0 */ - Native_M1, /* 02 FST_SPI_CLK */ - GPIO_NC, /* 03 FST_SPI_D3 */ - GPIO_NC, /* GPO FST_SPI_CS1_B */ - Native_M1, /* 05 FST_SPI_D1 */ - Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_NC, /* 07 FST_SPI_CS2_B */ - GPIO_NC, /* 15 UART1_RTS_B */ - Native_M2, /* 16 UART1_RXD */ - GPIO_NC, /* 17 UART2_RXD */ - GPIO_NC, /* 18 UART1_CTS_B */ - GPIO_NC, /* 19 UART2_RTS_B */ - Native_M2, /* 20 UART1_TXD */ - GPIO_NC, /* 21 UART2_TXD */ - GPIO_NC, /* 22 UART2_CTS_B */ - GPIO_NC, /* 30 MF_HDA_CLK */ - GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ - GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ - GPIO_NC, /* 33 MF_HDA_SDO */ - GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 34 MF_HDA_DOCKRSTB */ - GPIO_NC, /* 35 MF_HDA_SYNC */ - GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ - NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - GPIO_NC, /* 46 I2C4_SDA */ - NATIVE_PU20K(2), /* 47 I2C6_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ - GPIO_NC, /* 49 I2C_NFC_SDA */ - GPIO_NC, /* 50 I2C4_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ - GPIO_NC, /* 52 I2C_NFC_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ - GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ - NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ - GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ - GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPIO_NC, /* 76 GPI SATA_GP1 */ - GPIO_INPUT_PU_20K, /* 77 SATA_LEDN, EC_IN_RW */ - GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */ - Native_M1, /* 79 MF_SMB_ALERTB */ - GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ - Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ - /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ - Native_M1, /* 90 PCIE_CLKREQ0B */ - GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ - Native_M1, /* 92 GP_SSP_2_CLK */ - NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ - Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), - /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ - Native_M1, /* 96 GP_SSP_2_FS */ - NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ - GPIO_END -}; - - -/* North Community */ -static const struct soc_gpio_map gpn_gpio_map[] = { - GPIO_NC, /* 00 GPIO_DFX0 */ - GPIO_NC, /* 01 GPIO_DFX3 */ - GPIO_NC, /* 02 GPIO_DFX7 */ - GPIO_NC, /* 03 GPIO_DFX1 */ - GPIO_NC, /* 04 GPIO_DFX5 */ - GPIO_NC, /* 05 GPIO_DFX4 */ - GPIO_NC, /* 06 GPIO_DFX8 */ - GPIO_NC, /* 07 GPIO_DFX2 */ - GPIO_NC, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , - UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ - GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), - /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), - /* 19 GPIO_SUS1 */ - GPIO_NC, /* 20 GPIO_SUS5 */ - GPIO_NC, /* 21 SEC_GPIO_SUS11 */ - GPIO_NC, /* 22 GPIO_SUS4 */ - GPIO_NC, - /* 23 SEC_GPIO_SUS8 */ - Native_M6, /* 24 GPIO_SUS2 */ - GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ - Native_M1, /* 26 CX_PREQ_B */ - GPO_FUNC(0, 0), /* 27 SEC_GPIO_SUS9 */ - Native_M1, /* 30 TRST_B */ - Native_M1, /* 31 TCK */ - GPIO_SKIP, /* 32 PROCHOT_B */ - GPIO_SKIP, /* 33 SVID0_DATA */ - Native_M1, /* 34 TMS */ - GPIO_NC, /* 35 CX_PRDY_B_2 */ - GPIO_NC, /* 36 TDO_2 */ - Native_M1, /* 37 CX_PRDY_B */ - GPIO_SKIP, /* 38 SVID0_ALERT_B */ - Native_M1, /* 39 TDO */ - GPIO_SKIP, /* 40 SVID0_CLK */ - Native_M1, /* 41 TDI */ - Native_M2, /* 45 GP_CAMERASB05 */ - Native_M2, /* 46 GP_CAMERASB02 */ - Native_M2, /* 47 GP_CAMERASB08 */ - Native_M2, /* 48 GP_CAMERASB00 */ - Native_M2, /* 49 GP_CAMERASBO6 */ - GPIO_NC, /* 50 GP_CAMERASB10 */ - Native_M2, /* 51 GP_CAMERASB03 */ - GPIO_NC, /* 52 GP_CAMERASB09 */ - Native_M2, /* 53 GP_CAMERASB01 */ - Native_M2, /* 54 GP_CAMERASB07 */ - GPIO_NC, /* 55 GP_CAMERASB11 */ - Native_M2, /* 56 GP_CAMERASB04 */ - GPIO_NC, /* 60 PANEL0_BKLTEN */ - GPIO_NC, /* 61 HV_DDI0_HPD */ - NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ - Native_M1, /* 63 PANEL1_BKLTCTL */ - NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ - GPIO_NC, /* 65 PANEL0_BKLTCTL */ - GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ - NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ - NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ - Native_M1, /* 69 PANEL1_VDDEN */ - Native_M1, /* 70 PANEL1_BKLTEN */ - GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ - GPIO_NC, /* 72 PANEL0_VDDEN */ - GPIO_END -}; - - -/* East Community */ -static const struct soc_gpio_map gpe_gpio_map[] = { - Native_M1, /* 00 PMU_SLP_S3_B */ - GPIO_NC, /* 01 PMU_BATLOW_B */ - Native_M1, /* 02 SUS_STAT_B */ - Native_M1, /* 03 PMU_SLP_S0IX_B */ - Native_M1, /* 04 PMU_AC_PRESENT */ - Native_M1, /* 05 PMU_PLTRST_B */ - Native_M1, /* 06 PMU_SUSCLK */ - GPIO_NC, /* 07 PMU_SLP_LAN_B */ - Native_M1, /* 08 PMU_PWRBTN_B */ - Native_M1, /* 09 PMU_SLP_S4_B */ - NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ - GPIO_NC, /* 11 PMU_WAKE_LAN_B */ - GPIO_NC, /* 15 MF_GPIO_3 */ - GPIO_NC, /* 16 MF_GPIO_7 */ - GPIO_NC, /* 17 MF_I2C1_SCL */ - GPIO_NC, /* 18 MF_GPIO_1 */ - GPIO_NC, /* 19 MF_GPIO_5 */ - GPIO_NC, /* 20 MF_GPIO_9 */ - GPIO_NC, /* 21 MF_GPIO_0 */ - GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ - GPIO_NC, /* 23 MF_GPIO_8 */ - GPIO_NC, /* 24 MF_GPIO_2 */ - GPIO_NC, /* 25 MF_GPIO_6 */ - GPIO_NC, /* 26 MF_I2C1_SDA */ - GPIO_END -}; - - -static struct soc_gpio_config gpio_config = { - /* BSW */ - .north = gpn_gpio_map, - .southeast = gpse_gpio_map, - .southwest = gpsw_gpio_map, - .east = gpe_gpio_map -}; - -struct soc_gpio_config *mainboard_get_gpios(void) -{ - return &gpio_config; -} diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index 71ba62b13e..e5ad945b90 100644 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -15,9 +15,7 @@ * GNU General Public License for more details. */ -#include #include -#include #include #include "ec.h" diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h deleted file mode 100644 index c891aa8690..0000000000 --- a/src/mainboard/google/cyan/onboard.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -#include "irqroute.h" - -/* - * Calculation of gpio based irq. - * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE - * Max direct irq (MAX_DIRECT_IRQ) is 114. - * Size of gpio banks are - * GPSW_SIZE = 98 - * GPNC_SIZE = 73 - * GPEC_SIZE = 27 - * GPSE_SIZE = 86 - */ - -#define BOARD_TOUCH_IRQ 184 - -/* KBD: Gpio index in N bank */ -#define BOARD_I8042_GPIO_INDEX 17 -/* SCI: Gpio index in N bank */ -#define BOARD_SCI_GPIO_INDEX 15 -/* Trackpad: Gpio index in N bank */ -#define BOARD_TRACKPAD_GPIO_INDEX 18 -/* Touch: Gpio index in N bank */ -#define BOARD_TOUCH_GPIO_INDEX 19 -/* TI Audio: Gpio index in SW bank */ -#define BOARD_JACK_TI_GPIO_INDEX 34 -/* MAXIM Audio: Gpio index in SE bank */ -#define BOARD_JACK_MAXIM_GPIO_INDEX 77 - -#define BOARD_TRACKPAD_NAME "trackpad" -#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) -#define BOARD_TRACKPAD_I2C_BUS 5 -#define BOARD_TRACKPAD_I2C_ADDR 0x15 - -#define BOARD_TOUCHSCREEN_NAME "touchscreen" -#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) -#define BOARD_TOUCHSCREEN_I2C_BUS 0 -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ - - -/* SD CARD gpio */ -#define SDCARD_CD 81 - -#define AUDIO_CODEC_HID "193C9890" -#define AUDIO_CODEC_CID "193C9890" -#define AUDIO_CODEC_DDN "Maxim 98090 Codec " -#define AUDIO_CODEC_I2C_ADDR 0x10 - -#define TI_SWITCH_HID "104C227E" -#define TI_SWITCH_CID "104C227E" -#define TI_SWITCH_DDN "TI SWITCH " -#define TI_SWITCH_I2C_ADDR 0x3B - -#endif - -#define DPTF_CPU_PASSIVE 88 -#define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c index e247c984bd..093a49bf16 100644 --- a/src/mainboard/google/cyan/ramstage.c +++ b/src/mainboard/google/cyan/ramstage.c @@ -14,9 +14,8 @@ */ #include -#include -#include "onboard.h" +__attribute__ ((weak)) void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { } diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index 61ebde9529..28a8a46a39 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -14,13 +14,7 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include #include -#include /* All FSP specific code goes in this block */ void mainboard_romstage_entry(struct romstage_params *rp) @@ -33,6 +27,7 @@ void mainboard_romstage_entry(struct romstage_params *rp) romstage_common(rp); } +__attribute__ ((weak)) void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 98e4873a9b..75c1890d2c 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -25,7 +25,7 @@ #include #include -#include "onboard.h" +#include /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0 diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/spd/Makefile.inc deleted file mode 100644 index f5960863ae..0000000000 --- a/src/mainboard/google/cyan/spd/Makefile.inc +++ /dev/null @@ -1,42 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += spd.c - -SPD_BIN = $(obj)/spd.bin - -SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 -SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR -SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 -SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR -SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 -SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 -SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 -SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 0c0d4f5651..f38fc58ff8 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -26,24 +26,10 @@ #include #include #include +#include "spd_util.h" -/* - * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz - * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz - * 0b0010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz - * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz - * 0b0100 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz - * 0b0101 - 4GiB total - 2 x 2GiB Micro MT41K256M16TW-107 1600MHz - * 0b0110 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz - * 0b0111 - 2GiB total - 1 x 2GiB Micro MT41K256M16TW-107 1600MHz - */ -static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) - | (1 << 4) | (1 << 5); - -static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +__attribute__ ((weak)) uint8_t get_ramid(void) { - int ram_id = 0; - gpio_t spd_gpios[] = { GP_SW_80, /* SATA_GP3, RAMID0 */ GP_SW_67, /* I2C3_SCL, RAMID1 */ @@ -51,45 +37,24 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) GP_SW_64, /* I2C3_SDA, RAMID3 */ }; - ram_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); - if (ram_id >= total_spds) - return NULL; + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +{ + int ram_id = 0; + int spd_index = 0; - /* Determine if this is a single or dual channel memory system */ - if (dual_channel_config & (1 << ram_id)) - *dual = 1; + ram_id = get_ramid(); + printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); - /* Display the RAM type */ - switch (ram_id) { - case 0: - printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646Q-HYK0 1600MHz\n"); - break; - case 2: - printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646Q-HYK0 1600MHz\n"); - break; - case 1: - printk(BIOS_DEBUG, "4GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); - break; - case 3: - printk(BIOS_DEBUG, "2GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); - break; - case 4: - printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646E-BYK0 1600MHz\n"); - break; - case 5: - printk(BIOS_DEBUG, "4GiB Micro MT41K256M16TW-107 1600MHz\n"); - break; - case 6: - printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646E-BYK0 1600MHz\n"); - break; - case 7: - printk(BIOS_DEBUG, "2GiB Micro MT41K256M16TW-107 1600MHz\n"); - break; + spd_index = get_variant_spd_index(ram_id, dual); + if (spd_index >= total_spds) { + printk(BIOS_ERR, "SPD index > total SPDs\n"); + return NULL; } - /* Return the serial product data for the RAM */ - return &spd_file_content[SPD_PAGE_LEN * ram_id]; + return &spd_file_content[SPD_PAGE_LEN * spd_index]; } /* Copy SPD data for on-board memory */ diff --git a/src/mainboard/google/cyan/spd/spd_util.h b/src/mainboard/google/cyan/spd/spd_util.h new file mode 100644 index 0000000000..11d6eaa16d --- /dev/null +++ b/src/mainboard/google/cyan/spd/spd_util.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Matt DeVillier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SPD_UTIL_H +#define SPD_UTIL_H + +uint8_t get_ramid(void); +int get_variant_spd_index(int ram_id, int *dual); + +#endif /* SPD_UTIL_H */ diff --git a/src/mainboard/google/cyan/variants/cyan/Makefile.inc b/src/mainboard/google/cyan/variants/cyan/Makefile.inc new file mode 100644 index 0000000000..ea80446156 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/Makefile.inc @@ -0,0 +1,44 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c + +ramstage-y += gpio.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/cyan/board_info.txt b/src/mainboard/google/cyan/variants/cyan/board_info.txt new file mode 100644 index 0000000000..b1138cadac --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Cyan +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/cyan/variants/cyan/devicetree.cb b/src/mainboard/google/cyan/variants/cyan/devicetree.cb new file mode 100644 index 0000000000..0454650c68 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/devicetree.cb @@ -0,0 +1,143 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "1" + register "PcdCaMirrorEn" = "0" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_ACPI_MODE" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "1" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "1" + register "PcdEnableDma1" = "1" + register "PcdEnableI2C0" = "1" + register "PcdEnableI2C1" = "1" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "0" + register "PcdEnableI2C5" = "1" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "SVID_CONFIG1" + register "PcdEmmcMode" = "PCH_ACPI_MODE" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "0" # Disable SATA + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "3" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "1" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + + # LPE audio codec settings + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock + + # Enable devices in ACPI mode + register "lpss_acpi_mode" = "1" + register "emmc_acpi_mode" = "1" + register "sd_acpi_mode" = "1" + register "lpe_acpi_mode" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + # EDS Table 24-4, Figure 24-5 + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 off end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 on end # 8086 22dc - ? + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 11.0 off end # 8086 0F15 - SDIO Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 13.0 off end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 on end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 off end # 8086 22c5 - I2C Port 5 + device pci 18.6 on end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3 + device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.1 off end # 8086 0F08 - PWM 1 + device pci 1e.2 off end # 8086 0F09 - PWM 2 + device pci 1e.3 on end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1e.5 on end # 8086 228e - SPI 1 + device pci 1e.6 off end # 8086 2290 - SPI 2 + device pci 1e.7 off end # 8086 22ac - SPI 3 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Bridge + device pci 1f.3 off end # 8086 0F12 - SMBus 0 + end +end diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c new file mode 100644 index 0000000000..9e8c5d126b --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -0,0 +1,260 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + Native_M1, /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* SPI1_CS1_B 66 */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + /* GPIO_ALERT 77 */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + GPIO_NC, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPIO_NC, /* 82 spkr asummed gpio number */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN,/* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + GPIO_NC, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + GPIO_NC, /* 03 FST_SPI_D3 */ + GPIO_NC, /* GPO FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + Native_M2, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + Native_M2, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + GPIO_NC, /* 30 MF_HDA_CLK */ + GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ + GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + GPIO_NC, /* 33 MF_HDA_SDO */ + GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 34 MF_HDA_DOCKRSTB */ + GPIO_NC, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU20K(2), /* 47 I2C6_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ + GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ + GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ + GPIO_OUT_HIGH, /* 75 SATA_GP0 */ + GPIO_NC, /* 76 GPI SATA_GP1 */ + GPIO_INPUT_PU_20K, /* 77 SATA_LEDN, EC_IN_RW */ + GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */ + Native_M1, /* 79 MF_SMB_ALERTB */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ + Native_M1, /* 92 GP_SSP_2_CLK */ + NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + Native_M1, /* 94 GP_SSP_2_RXD */ + GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + Native_M1, /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + GPIO_NC, /* 00 GPIO_DFX0 */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPIO_NC, /* 03 GPIO_DFX1 */ + GPIO_NC, /* 04 GPIO_DFX5 */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPIO_NC, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPIO_NC, /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, + /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPO_FUNC(0, 0), /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + Native_M2, /* 45 GP_CAMERASB05 */ + Native_M2, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + Native_M2, /* 48 GP_CAMERASB00 */ + Native_M2, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + Native_M2, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + Native_M2, /* 53 GP_CAMERASB01 */ + Native_M2, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + Native_M2, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + GPIO_NC, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..3c8dbe4a52 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 49 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 85 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 49 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x400, "mA", 0 }, /* 1.0A (MAX) */ + Package () { 0, 0, 0, 0, 12, 0x300, "mA", 0 }, /* 0.77A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 4, 0x100, "mA", 0 }, /* 0.25A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 2000, /* PowerLimitMinimum */ + 6200, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..e9b16fcf78 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Matt DeVillier + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan touchscreen */ +#include + +/* Elan trackpad */ +#include + +/* Maxim audio codec */ +#include diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h new file mode 100644 index 0000000000..a27e47d511 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +#define BOARD_TOUCH_IRQ 184 + +/* KBD: Gpio index in N bank */ +#define BOARD_I8042_GPIO_INDEX 17 +/* SCI: Gpio index in N bank */ +#define BOARD_SCI_GPIO_INDEX 15 +/* Trackpad: Gpio index in N bank */ +#define BOARD_TRACKPAD_GPIO_INDEX 18 +/* Touch: Gpio index in N bank */ +#define BOARD_TOUCH_GPIO_INDEX 19 +/* TI Audio: Gpio index in SW bank */ +#define BOARD_JACK_TI_GPIO_INDEX 34 +/* MAXIM Audio: Gpio index in SE bank */ +#define BOARD_JACK_MAXIM_GPIO_INDEX 77 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 + + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "193C9890" +#define AUDIO_CODEC_CID "193C9890" +#define AUDIO_CODEC_DDN "Maxim 98090 Codec " +#define AUDIO_CODEC_I2C_ADDR 0x10 + +#define TI_SWITCH_HID "104C227E" +#define TI_SWITCH_CID "104C227E" +#define TI_SWITCH_DDN "TI SWITCH " +#define TI_SWITCH_I2C_ADDR 0x3B + +#define DPTF_CPU_PASSIVE 88 +#define DPTF_CPU_CRITICAL 90 + +#endif diff --git a/src/mainboard/google/cyan/variants/cyan/spd_util.c b/src/mainboard/google/cyan/variants/cyan/spd_util.c new file mode 100644 index 0000000000..63a1df3760 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/spd_util.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Matt DeVillier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/* + * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b0010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b0100 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz + * 0b0101 - 4GiB total - 2 x 2GiB Micron MT41K256M16TW-107 1600MHz + * 0b0110 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz + * 0b0111 - 2GiB total - 1 x 2GiB Micron MT41K256M16TW-107 1600MHz + */ + +int get_variant_spd_index(int ram_id, int *dual) +{ + /* Determine if single or dual channel memory system */ + /* RAMID1 is deterministic for cyan */ + *dual = ((ram_id > 1) & 0x1) ? 0 : 1; + + /* Display the RAM type */ + switch (ram_id) { + case 0: + printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646Q-HYK0 1600MHz\n"); + break; + case 1: + printk(BIOS_DEBUG, "4GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); + break; + case 2: + printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646Q-HYK0 1600MHz\n"); + break; + case 3: + printk(BIOS_DEBUG, "2GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); + break; + case 4: + printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646E-BYK0 1600MHz\n"); + break; + case 5: + printk(BIOS_DEBUG, "4GiB Micron MT41K256M16TW-107 1600MHz\n"); + break; + case 6: + printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646E-BYK0 1600MHz\n"); + break; + case 7: + printk(BIOS_DEBUG, "2GiB Micron MT41K256M16TW-107 1600MHz\n"); + break; + } + + /* 1:1 mapping between ram_id and spd_index for cyan */ + return ram_id; +} -- cgit v1.2.3