From e68650a656e185c7b056d62a79611ec2ad93e7dd Mon Sep 17 00:00:00 2001
From: Jeremy Compostella <jeremy.compostella@intel.com>
Date: Wed, 18 Oct 2023 12:39:10 -0700
Subject: vc/intel/fsp/mtl: Add Psi[1-3]Threshold UPDs to FSP-M header file
Export Power State Current 1, 2 and 3 Threshold configuration entries.
BUG=b:308002192
Change-Id: Iff4467720541efbdedace12431cd1f6f66fca8e6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
.../intel/fsp/fsp2_0/meteorlake/FspmUpd.h | 25 ++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
(limited to 'src')
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
index c2b2708883..7853004998 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
@@ -1442,9 +1442,30 @@ typedef struct {
**/
UINT16 DcLoadline[6];
-/** Offset 0x063C - Reserved
+/** Offset 0x063C - Power State 1 Threshold current
+ PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range
+ 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA,
+ [3] through [5] are Reserved.
**/
- UINT8 Reserved34[90];
+ UINT16 Psi1Threshold[6];
+
+/** Offset 0x0648 - Power State 2 Threshold current
+ PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range
+ 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA,
+ [3] through [5] are Reserved.
+**/
+ UINT16 Psi2Threshold[6];
+
+/** Offset 0x0654 - Power State 3 Threshold current
+ PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range
+ 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA,
+ [3] through [5] are Reserved.
+**/
+ UINT16 Psi3Threshold[6];
+
+/** Offset 0x0660 - Reserved
+**/
+ UINT8 Reserved34[54];
/** Offset 0x0696 - Thermal Design Current enable/disable
Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
--
cgit v1.2.3