From e64b63750f029dac66902dee8cf6a7cf82ba44a3 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 8 Apr 2010 21:04:45 +0000 Subject: Split crt0.S.lb into prologue and epilogue (the latter only for romcc), rename crt0_includes.h to crt0.S, and compile that directly. Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/arch/i386/Makefile.bigbootblock.inc | 4 +- src/arch/i386/Makefile.bootblock.inc | 4 +- src/arch/i386/Makefile.inc | 6 +- src/arch/i386/init/crt0.S.lb | 147 ----------------------------- src/arch/i386/init/crt0_prologue.inc | 28 ++++++ src/arch/i386/init/crt0_romcc_epilogue.inc | 124 ++++++++++++++++++++++++ 6 files changed, 161 insertions(+), 152 deletions(-) delete mode 100644 src/arch/i386/init/crt0.S.lb create mode 100644 src/arch/i386/init/crt0_prologue.inc create mode 100644 src/arch/i386/init/crt0_romcc_epilogue.inc (limited to 'src') diff --git a/src/arch/i386/Makefile.bigbootblock.inc b/src/arch/i386/Makefile.bigbootblock.inc index fc9b0ec584..1ecdd78deb 100644 --- a/src/arch/i386/Makefile.bigbootblock.inc +++ b/src/arch/i386/Makefile.bigbootblock.inc @@ -16,7 +16,7 @@ $(obj)/ldscript.ld: $$(ldscripts) $(obj)/ldoptions printf 'INCLUDE "ldoptions"\n' > $@ printf '$(foreach ldscript,$(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@ -$(obj)/crt0_includes.h: $$(crt0s) +$(obj)/crt0.S: $$(crt0s) @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ @@ -24,7 +24,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.initobj.o: $(obj)/mainboard/$(MAINBOARDDIR @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $@)/crt0.disasm -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/crt0_includes.h +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/crt0.S @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ diff --git a/src/arch/i386/Makefile.bootblock.inc b/src/arch/i386/Makefile.bootblock.inc index 5c4a5f6a1a..fae8e2060c 100644 --- a/src/arch/i386/Makefile.bootblock.inc +++ b/src/arch/i386/Makefile.bootblock.inc @@ -96,7 +96,7 @@ $(obj)/romstage/ldscript.ld: $$(ldscripts) $(obj)/ldoptions mkdir -p $(obj)/romstage printf '$(foreach ldscript,ldoptions location.ld $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' > $@ -$(obj)/romstage/crt0_includes.h: $$(crt0s) +$(obj)/romstage/crt0.S: $$(crt0s) @printf " GEN $(subst $(obj)/,,$(@))\n" mkdir -p $(obj)/romstage printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ @@ -105,7 +105,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.initobj.o: $(obj)/mainboard/$(MAINBOARDDIR @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $@)/crt0.disasm -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/romstage/crt0_includes.h +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ diff --git a/src/arch/i386/Makefile.inc b/src/arch/i386/Makefile.inc index d1cb806049..a8f6a005a6 100644 --- a/src/arch/i386/Makefile.inc +++ b/src/arch/i386/Makefile.inc @@ -100,7 +100,7 @@ endif ####################################################################### # done -crt0s = +crt0s = $(src)/arch/i386/init/crt0_prologue.inc ldscripts = ldscripts += $(src)/arch/i386/init/ldscript_fallback_cbfs.lb ifeq ($(CONFIG_BIG_BOOTBLOCK),y) @@ -196,6 +196,10 @@ crt0s += $(chipset_bootblock_inc) ldscripts += $(chipset_bootblock_lds) endif +ifeq ($(CONFIG_ROMCC),y) +crt0s += $(src)/arch/i386/init/crt0_romcc_epilogue.inc +endif + OPTION_TABLE_H:= ifeq ($(CONFIG_HAVE_OPTION_TABLE),y) OPTION_TABLE_H:=$(obj)/option_table.h diff --git a/src/arch/i386/init/crt0.S.lb b/src/arch/i386/init/crt0.S.lb deleted file mode 100644 index 5e7a5fa8c7..0000000000 --- a/src/arch/i386/init/crt0.S.lb +++ /dev/null @@ -1,147 +0,0 @@ -/* -*- asm -*- - * $ $ - * - */ - -/* - * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer - * - * This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * Originally this code was part of ucl the data compression library - * for upx the ``Ultimate Packer of eXecutables''. - * - * - Converted to gas assembly, and refitted to work with etherboot. - * Eric Biederman 20 Aug 2002 - * - Merged the nrv2b decompressor into crt0.base of coreboot - * Eric Biederman 26 Sept 2002 - */ - - -#include -#include -#include - -#ifndef ASM_CONSOLE_LOGLEVEL -#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -#endif - -/* - * This is the entry code the code in .reset section - * jumps to this address. - * - */ -.section ".rom.data", "a", @progbits -.section ".rom.text", "ax", @progbits - - post_code(0x01) /* delay for chipsets */ - -#include "crt0_includes.h" - -#if CONFIG_USE_DCACHE_RAM == 0 -#ifndef CONSOLE_DEBUG_TX_STRING - /* uses: esp, ebx, ax, dx */ -# define __CRT_CONSOLE_TX_STRING(string) \ - mov string, %ebx ; \ - CALLSP(crt_console_tx_string) - -# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) -# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string) -# else -# define CONSOLE_DEBUG_TX_STRING(string) -# endif -#endif - - /* clear boot_complete flag */ - xorl %ebp, %ebp -__main: - CONSOLE_DEBUG_TX_STRING($str_copying_to_ram) - - /* - * Copy data into RAM and clear the BSS. Since these segments - * isn\'t really that big we just copy/clear using bytes, not - * double words. - */ - post_code(0x11) /* post 11 */ - - cld /* clear direction flag */ - - /* copy coreboot from it's initial load location to - * the location it is compiled to run at. - * Normally this is copying from FLASH ROM to RAM. - */ - movl %ebp, %esi - /* FIXME: look for a proper place for the stack */ - movl $0x4000000, %esp - movl %esp, %ebp - pushl %esi - pushl $str_coreboot_ram_name - call cbfs_and_run_core - -.Lhlt: - post_code(0xee) /* post fe */ - hlt - jmp .Lhlt - -#ifdef __CRT_CONSOLE_TX_STRING - /* Uses esp, ebx, ax, dx */ -crt_console_tx_string: - mov (%ebx), %al - inc %ebx - cmp $0, %al - jne 9f - RETSP -9: -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif -/* Data */ -#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00) - -/* Control */ -#define TTYS0_TBR TTYS0_RBR -#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01) -#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02) -#define TTYS0_FCR TTYS0_IIR -#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03) -#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04) -#define TTYS0_DLL TTYS0_RBR -#define TTYS0_DLM TTYS0_IER - -/* Status */ -#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05) -#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06) -#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07) - - mov %al, %ah -10: mov $TTYS0_LSR, %dx - inb %dx, %al - test $0x20, %al - je 10b - mov $TTYS0_TBR, %dx - mov %ah, %al - outb %al, %dx - - jmp crt_console_tx_string -#endif /* __CRT_CONSOLE_TX_STRING */ - -#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) -.section ".rom.data" -#if CONFIG_COMPRESS -str_copying_to_ram: .string "Uncompressing coreboot to RAM.\r\n" -#else -str_copying_to_ram: .string "Copying coreboot to RAM.\r\n" -#endif -str_pre_main: .string "Jumping to coreboot.\r\n" -.previous - -#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ - -str_coreboot_ram_name: .ascii CONFIG_CBFS_PREFIX - .string "/coreboot_ram" - -#endif /* CONFIG_USE_DCACHE_RAM */ diff --git a/src/arch/i386/init/crt0_prologue.inc b/src/arch/i386/init/crt0_prologue.inc new file mode 100644 index 0000000000..b0ce2cf869 --- /dev/null +++ b/src/arch/i386/init/crt0_prologue.inc @@ -0,0 +1,28 @@ +/* + * Copyright 2002 Eric Biederman + * + * This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + + +#include +#include +#include + +#ifndef ASM_CONSOLE_LOGLEVEL +#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +#endif + +/* + * This is the entry code the code in .reset section + * jumps to this address. + * + */ +.section ".rom.data", "a", @progbits +.section ".rom.text", "ax", @progbits + + post_code(0x01) /* delay for chipsets */ + diff --git a/src/arch/i386/init/crt0_romcc_epilogue.inc b/src/arch/i386/init/crt0_romcc_epilogue.inc new file mode 100644 index 0000000000..a8a6043830 --- /dev/null +++ b/src/arch/i386/init/crt0_romcc_epilogue.inc @@ -0,0 +1,124 @@ +/* -*- asm -*- + * $ $ + * + */ + +/* + * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer + * + * This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * Originally this code was part of ucl the data compression library + * for upx the ``Ultimate Packer of eXecutables''. + * + * - Converted to gas assembly, and refitted to work with etherboot. + * Eric Biederman 20 Aug 2002 + * - Merged the nrv2b decompressor into crt0.base of coreboot + * Eric Biederman 26 Sept 2002 + */ + + +#ifndef CONSOLE_DEBUG_TX_STRING + /* uses: esp, ebx, ax, dx */ +# define __CRT_CONSOLE_TX_STRING(string) \ + mov string, %ebx ; \ + CALLSP(crt_console_tx_string) + +# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) +# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string) +# else +# define CONSOLE_DEBUG_TX_STRING(string) +# endif +#endif + + /* clear boot_complete flag */ + xorl %ebp, %ebp +__main: + CONSOLE_DEBUG_TX_STRING($str_copying_to_ram) + + /* + * Copy data into RAM and clear the BSS. Since these segments + * isn\'t really that big we just copy/clear using bytes, not + * double words. + */ + post_code(0x11) /* post 11 */ + + cld /* clear direction flag */ + + /* copy coreboot from it's initial load location to + * the location it is compiled to run at. + * Normally this is copying from FLASH ROM to RAM. + */ + movl %ebp, %esi + /* FIXME: look for a proper place for the stack */ + movl $0x4000000, %esp + movl %esp, %ebp + pushl %esi + pushl $str_coreboot_ram_name + call cbfs_and_run_core + +.Lhlt: + post_code(0xee) /* post fe */ + hlt + jmp .Lhlt + +#ifdef __CRT_CONSOLE_TX_STRING + /* Uses esp, ebx, ax, dx */ +crt_console_tx_string: + mov (%ebx), %al + inc %ebx + cmp $0, %al + jne 9f + RETSP +9: +/* Base Address */ +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3f8 +#endif +/* Data */ +#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00) + +/* Control */ +#define TTYS0_TBR TTYS0_RBR +#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01) +#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02) +#define TTYS0_FCR TTYS0_IIR +#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03) +#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04) +#define TTYS0_DLL TTYS0_RBR +#define TTYS0_DLM TTYS0_IER + +/* Status */ +#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05) +#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06) +#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07) + + mov %al, %ah +10: mov $TTYS0_LSR, %dx + inb %dx, %al + test $0x20, %al + je 10b + mov $TTYS0_TBR, %dx + mov %ah, %al + outb %al, %dx + + jmp crt_console_tx_string +#endif /* __CRT_CONSOLE_TX_STRING */ + +#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) +.section ".rom.data" +#if CONFIG_COMPRESS +str_copying_to_ram: .string "Uncompressing coreboot to RAM.\r\n" +#else +str_copying_to_ram: .string "Copying coreboot to RAM.\r\n" +#endif +str_pre_main: .string "Jumping to coreboot.\r\n" +.previous + +#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ + +str_coreboot_ram_name: .ascii CONFIG_CBFS_PREFIX + .string "/coreboot_ram" -- cgit v1.2.3