From e5cecd0ea42b52ac59cb75abe1bdcc83f391e9bf Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 27 Aug 2017 20:50:08 +0530 Subject: soc/intel/skylake: Fix FSP1.1 booting issue with HW based dram top calculation This patch ensures skylake device using FSP1.1 can use HW based DRAM top calculation which was broken due to skylake fsp1.1 not honoring any UPD to know PRMMR size and default reserving 1MB for PRMRR size. This WA is not needed for FSP2.0 implementation due to PrmrrSize UPD is available and considering into hw based dram top calculation. BRANCH=none BUG=b:63974384 TEST=Build and boot lars which is using skylake 1.1 fsp. Change-Id: Iade0d2cb2a290fc4c9f0e6b1eaadc8afff2fa581 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/21224 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Matt DeVillier --- src/soc/intel/skylake/memmap.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index d5d372484c..1ccaf1d3b8 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -178,7 +178,10 @@ static u32 calculate_dram_base(void) dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)); config = dev->chip_info; - prmrr_size = config->PrmrrSize; + if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) + prmrr_size = 1*MiB; + else + prmrr_size = config->PrmrrSize; if (prmrr_size > 0) { /* -- cgit v1.2.3