From e59f70a4d912c64c4b6fdd30c08fcea868da98bc Mon Sep 17 00:00:00 2001
From: John Su <john_su@compal.corp-partner.google.com>
Date: Wed, 18 Nov 2020 13:47:43 +0800
Subject: mb/google/dedede/variants/madoo: Increase TCC offset from 5 to 10

Increase TCC offset value from 5 to 10 for Thermal Control Circuit (TCC)
activation.

BUG=b:171531244
TEST=build and verify by thermal team

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ic2822b059f166779e1f0bcf92e753dad1078783c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47691
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/google/dedede/variants/madoo/overridetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
index 1be1012123..c7f39952c5 100644
--- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
@@ -59,7 +59,7 @@ chip soc/intel/jasperlake
 			.tdp_pl2_override = 20,
 	}"
 
-	register "tcc_offset" = "5"    # TCC of 95C
+	register "tcc_offset" = "10"    # TCC of 95C
 
 	device domain 0 on
 		device pci 04.0 on
-- 
cgit v1.2.3