From e4d73ec578e74495ab91279300f9d1dd61df349b Mon Sep 17 00:00:00 2001 From: Jian Tong Date: Wed, 22 May 2024 10:43:27 +0800 Subject: mb/google/brox/var/lotso: Add dq map setting Based on lotso EVT schematics add dq map settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I4f03e8a90522cbf2fe06f4160414202dcc4a2199 Signed-off-by: Jian Tong Reviewed-on: https://review.coreboot.org/c/coreboot/+/82600 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Eric Lai Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen Reviewed-by: Dengwu Yu --- .../google/brox/variants/lotso/Makefile.mk | 1 + src/mainboard/google/brox/variants/lotso/memory.c | 103 +++++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 src/mainboard/google/brox/variants/lotso/memory.c (limited to 'src') diff --git a/src/mainboard/google/brox/variants/lotso/Makefile.mk b/src/mainboard/google/brox/variants/lotso/Makefile.mk index 91f031e7a4..48683172d6 100644 --- a/src/mainboard/google/brox/variants/lotso/Makefile.mk +++ b/src/mainboard/google/brox/variants/lotso/Makefile.mk @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brox/variants/lotso/memory.c b/src/mainboard/google/brox/variants/lotso/memory.c new file mode 100644 index 0000000000..0765d5e57e --- /dev/null +++ b/src/mainboard/google/brox/variants/lotso/memory.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + /* Leave Rcomp unspecified to use the FSP optimized defaults */ + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 13, 15, 14, 12, 11, 9, 10, 8 }, + .dq1 = { 3, 0, 2, 1, 6, 7, 5, 4 }, + }, + .ddr1 = { + .dq0 = { 2, 0, 1, 3, 6, 4, 7, 5 }, + .dq1 = { 13, 15, 12, 14, 10, 11, 8, 9 }, + }, + .ddr2 = { + .dq0 = { 14, 13, 12, 15, 9, 10, 11, 8 }, + .dq1 = { 4, 6, 7, 5, 1, 2, 0, 3 }, + }, + .ddr3 = { + .dq0 = { 14, 13, 15, 12, 8, 11, 9, 10 }, + .dq1 = { 0, 2, 1, 3, 6, 5, 7, 4 }, + }, + .ddr4 = { + .dq0 = { 8, 11, 10, 9, 14, 15, 13, 12 }, + .dq1 = { 3, 0, 2, 1, 5, 7, 4, 6 }, + }, + .ddr5 = { + .dq0 = { 2, 1, 3, 0, 6, 4, 7, 5 }, + .dq1 = { 12, 13, 15, 14, 10, 9, 8, 11 }, + }, + .ddr6 = { + .dq0 = { 1, 0, 3, 2, 5, 7, 6, 4 }, + .dq1 = { 15, 13, 12, 14, 8, 11, 10, 9 }, + }, + .ddr7 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6 }, + .dq1 = { 14, 15, 9, 11, 12, 8, 10, 13 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .LpDdrDqDqsReTraining = 1, + + .ect = 1, /* Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * MEM_STRAP_0 GPP_S4 + * MEM_STRAP_1 GPP_S5 + * MEM_STRAP_2 GPP_S6 + * MEM_STRAP_3 GPP_S7 + */ + gpio_t spd_gpios[] = { + GPP_S4, + GPP_S5, + GPP_S6, + GPP_S7, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* MEM_CH_SEL GPP_S0 */ + return gpio_get(GPP_S0); +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} -- cgit v1.2.3