From e4156c33bdce1a705769f560263bd6640236702f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 14 Sep 2020 15:47:59 +0200 Subject: nb/intel/haswell: Move register headers into a subfolder Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I143b3c829be44a39e14902255cd4bb13bf02f0c1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45354 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/haswell.h | 4 +- src/northbridge/intel/haswell/hostbridge_regs.h | 71 ---------------------- src/northbridge/intel/haswell/mchbar_regs.h | 47 -------------- .../intel/haswell/registers/host_bridge.h | 71 ++++++++++++++++++++++ src/northbridge/intel/haswell/registers/mchbar.h | 47 ++++++++++++++ 5 files changed, 120 insertions(+), 120 deletions(-) delete mode 100644 src/northbridge/intel/haswell/hostbridge_regs.h delete mode 100644 src/northbridge/intel/haswell/mchbar_regs.h create mode 100644 src/northbridge/intel/haswell/registers/host_bridge.h create mode 100644 src/northbridge/intel/haswell/registers/mchbar.h (limited to 'src') diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 49e31a8e66..136701cca2 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -18,7 +18,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#include "hostbridge_regs.h" +#include "registers/host_bridge.h" /* Device 0:2.0 PCI configuration space (Graphics Device) */ @@ -43,7 +43,7 @@ #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* As there are many registers, define them on a separate file */ -#include "mchbar_regs.h" +#include "registers/mchbar.h" #define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ #define DMAR_LCKDN (1 << 31) diff --git a/src/northbridge/intel/haswell/hostbridge_regs.h b/src/northbridge/intel/haswell/hostbridge_regs.h deleted file mode 100644 index 70e15b74e2..0000000000 --- a/src/northbridge/intel/haswell/hostbridge_regs.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __HASWELL_HOSTBRIDGE_REGS_H__ -#define __HASWELL_HOSTBRIDGE_REGS_H__ - -#define EPBAR 0x40 -#define MCHBAR 0x48 - -#define GGC 0x50 /* GMCH Graphics Control */ -#define GGC_DISABLE_VGA_IO_DECODE (1 << 1) -#define GGC_IGD_MEM_IN_32MB_UNITS(x) (((x) & 0x1f) << 3) -#define GGC_GTT_0MB (0 << 8) -#define GGC_GTT_1MB (1 << 8) -#define GGC_GTT_2MB (2 << 8) - -#define DEVEN 0x54 /* Device Enable */ -#define DEVEN_D7EN (1 << 14) -#define DEVEN_D4EN (1 << 7) -#define DEVEN_D3EN (1 << 5) -#define DEVEN_D2EN (1 << 4) -#define DEVEN_D1F0EN (1 << 3) -#define DEVEN_D1F1EN (1 << 2) -#define DEVEN_D1F2EN (1 << 1) -#define DEVEN_D0EN (1 << 0) - -#define PAVPC 0x58 -#define DPR 0x5c - -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 - -#define MESEG_BASE 0x70 /* Management Engine Base */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit */ - -#define PAM0 0x80 -#define PAM1 0x81 -#define PAM2 0x82 -#define PAM3 0x83 -#define PAM4 0x84 -#define PAM5 0x85 -#define PAM6 0x86 - -#define LAC 0x87 /* Legacy Access Control */ -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - -#define REMAPBASE 0x90 /* Remap base */ -#define REMAPLIMIT 0x98 /* Remap limit */ -#define TOM 0xa0 /* Top of DRAM in memory controller space */ -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ -#define BDSM 0xb0 /* Base Data Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ - -#define SKPAD 0xdc /* Scratchpad Data */ - -#define CAPID0_A 0xe4 -#define CAPID_ECCDIS (1 << 25) -#define VTD_DISABLE (1 << 23) -#define CAPID_DDPCD (1 << 14) -#define CAPID_PDCD (1 << 12) -#define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) - -#define CAPID0_B 0xe8 - -#endif /* __HASWELL_HOSTBRIDGE_REGS_H__ */ diff --git a/src/northbridge/intel/haswell/mchbar_regs.h b/src/northbridge/intel/haswell/mchbar_regs.h deleted file mode 100644 index 5fe15567e5..0000000000 --- a/src/northbridge/intel/haswell/mchbar_regs.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __HASWELL_MCHBAR_REGS_H__ -#define __HASWELL_MCHBAR_REGS_H__ - -/* Register definitions */ -#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ -#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ -#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ -#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on HSW) */ -#define MC_INIT_STATE_G 0x5030 -#define MRC_REVISION 0x5034 /* MRC Revision */ - -#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ - -#define GFXVTBAR 0x5400 /* Base address for IGD */ -#define EDRAMBAR 0x5408 /* Base address for eDRAM */ -#define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */ -#define INTRDIRCTL 0x5418 /* Interrupt Redirection Control (PAIR) */ -#define GDXCBAR 0x5420 /* Generic Debug eXternal Connection */ - -/* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ -#define MMIO_PAVP_MSG 0x5500 - -/* Some power MSRs are also represented in MCHBAR */ -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 - -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -#define SSKPD 0x5d10 /* 64-bit scratchpad register */ -#define BIOS_RESET_CPL 0x5da8 /* 8-bit */ - -#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ -#define SAPMCTL 0x5f00 - -#define HDAUDRID 0x6008 -#define UMAGFXCTL 0x6020 -#define VDMBDFBARKVM 0x6030 -#define VDMBDFBARPAVP 0x6034 -#define VTDTRKLCK 0x63fc -#define REQLIM 0x6800 -#define DMIVCLIM 0x7000 -#define CRDTLCK 0x77fc - -#endif /* __HASWELL_MCHBAR_REGS_H__ */ diff --git a/src/northbridge/intel/haswell/registers/host_bridge.h b/src/northbridge/intel/haswell/registers/host_bridge.h new file mode 100644 index 0000000000..d348fd4a61 --- /dev/null +++ b/src/northbridge/intel/haswell/registers/host_bridge.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __HASWELL_REGISTERS_HOST_BRIDGE_H__ +#define __HASWELL_REGISTERS_HOST_BRIDGE_H__ + +#define EPBAR 0x40 +#define MCHBAR 0x48 + +#define GGC 0x50 /* GMCH Graphics Control */ +#define GGC_DISABLE_VGA_IO_DECODE (1 << 1) +#define GGC_IGD_MEM_IN_32MB_UNITS(x) (((x) & 0x1f) << 3) +#define GGC_GTT_0MB (0 << 8) +#define GGC_GTT_1MB (1 << 8) +#define GGC_GTT_2MB (2 << 8) + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D7EN (1 << 14) +#define DEVEN_D4EN (1 << 7) +#define DEVEN_D3EN (1 << 5) +#define DEVEN_D2EN (1 << 4) +#define DEVEN_D1F0EN (1 << 3) +#define DEVEN_D1F1EN (1 << 2) +#define DEVEN_D1F2EN (1 << 1) +#define DEVEN_D0EN (1 << 0) + +#define PAVPC 0x58 +#define DPR 0x5c + +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 + +#define MESEG_BASE 0x70 /* Management Engine Base */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit */ + +#define PAM0 0x80 +#define PAM1 0x81 +#define PAM2 0x82 +#define PAM3 0x83 +#define PAM4 0x84 +#define PAM5 0x85 +#define PAM6 0x86 + +#define LAC 0x87 /* Legacy Access Control */ +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +#define REMAPBASE 0x90 /* Remap base */ +#define REMAPLIMIT 0x98 /* Remap limit */ +#define TOM 0xa0 /* Top of DRAM in memory controller space */ +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#define BDSM 0xb0 /* Base Data Stolen Memory */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ + +#define SKPAD 0xdc /* Scratchpad Data */ + +#define CAPID0_A 0xe4 +#define CAPID_ECCDIS (1 << 25) +#define VTD_DISABLE (1 << 23) +#define CAPID_DDPCD (1 << 14) +#define CAPID_PDCD (1 << 12) +#define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) + +#define CAPID0_B 0xe8 + +#endif /* __HASWELL_REGISTERS_HOST_BRIDGE_H__ */ diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h new file mode 100644 index 0000000000..d6e59abe02 --- /dev/null +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __HASWELL_REGISTERS_MCHBAR_H__ +#define __HASWELL_REGISTERS_MCHBAR_H__ + +/* Register definitions */ +#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ +#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ +#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ +#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on HSW) */ +#define MC_INIT_STATE_G 0x5030 +#define MRC_REVISION 0x5034 /* MRC Revision */ + +#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ + +#define GFXVTBAR 0x5400 /* Base address for IGD */ +#define EDRAMBAR 0x5408 /* Base address for eDRAM */ +#define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */ +#define INTRDIRCTL 0x5418 /* Interrupt Redirection Control (PAIR) */ +#define GDXCBAR 0x5420 /* Generic Debug eXternal Connection */ + +/* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ +#define MMIO_PAVP_MSG 0x5500 + +/* Some power MSRs are also represented in MCHBAR */ +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 + +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define SSKPD 0x5d10 /* 64-bit scratchpad register */ +#define BIOS_RESET_CPL 0x5da8 /* 8-bit */ + +#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ +#define SAPMCTL 0x5f00 + +#define HDAUDRID 0x6008 +#define UMAGFXCTL 0x6020 +#define VDMBDFBARKVM 0x6030 +#define VDMBDFBARPAVP 0x6034 +#define VTDTRKLCK 0x63fc +#define REQLIM 0x6800 +#define DMIVCLIM 0x7000 +#define CRDTLCK 0x77fc + +#endif /* __HASWELL_REGISTERS_MCHBAR_H__ */ -- cgit v1.2.3