From e13a269f589b0ede64c24bb8cf7644a92d05792a Mon Sep 17 00:00:00 2001
From: Kane Chen <kane.chen@intel.com>
Date: Tue, 9 Jan 2018 09:52:37 +0800
Subject: mb/google/fizz: Disable PCH Lan

Fizz has external Lan on PCIE port.
The Lan device on PCH is not used.

BUG=b:70889517
Change-Id: I99894bedec14a44724ac7c22d0c894132a795b78
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/mainboard/google/fizz/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 189f49f93f..a3ae44c6b0 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -55,7 +55,7 @@ chip soc/intel/skylake
 
 	# FSP Configuration
 	register "ProbelessTrace" = "0"
-	register "EnableLan" = "1"
+	register "EnableLan" = "0"
 	register "EnableSata" = "1"
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
-- 
cgit v1.2.3