From e124fa5a9d48d7248a1a1987805b9c1ac2bdbde8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 12 Jan 2019 11:48:37 +0100 Subject: drivers/intel/fsp1_1: Print the MTRR's FSP-T set up MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I19e9038eb52922fa0c248936438f27789d00ddb5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/30876 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki --- src/drivers/intel/fsp1_1/car.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 79dd3681c3..3a41e40468 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -64,6 +64,8 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params) printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist); printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc); + display_mtrrs(); + if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE || car_params->bootloader_car_end != (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) { -- cgit v1.2.3