From e0cdaf0b19b68644b6c398be825f94327572e056 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 6 Dec 2019 19:37:37 +0530 Subject: soc/intel/tigerlake: add soc implementation for ETR address API Add soc_pmc_etr_addr function definition in tigerlake SOC code. The function is declared in common soc intel pmc driver. Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/37555 Reviewed-by: Maulik V Vaghela Reviewed-by: Wonkyu Kim Reviewed-by: Ravishankar Sarawadi Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/pmutil.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src') diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 53f86097ee..c163dc2f12 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -177,6 +177,12 @@ uintptr_t soc_read_pmc_base(void) return (uintptr_t)pmc_mmio_regs(); } + +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_tigerlake_config *config; -- cgit v1.2.3