From dfe817e45165fdbb8f4f7f83de83710cc46e75d6 Mon Sep 17 00:00:00 2001
From: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Date: Tue, 22 Mar 2022 20:00:29 +0530
Subject: sc7280: Improve performance by removing delays in cpucp init
As cpucp prepare takes 300 msec moving to before ramstage
BUG=b:218406702
TEST=Validated on qualcomm sc7280 development board observed
total timestamp as 1.73 sec from 1.97 sec
Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb
Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
---
src/mainboard/google/herobrine/romstage.c | 2 ++
src/soc/qualcomm/sc7280/Makefile.inc | 1 +
src/soc/qualcomm/sc7280/cpucp_load_reset.c | 9 ++++-----
3 files changed, 7 insertions(+), 5 deletions(-)
(limited to 'src')
diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c
index 2ea78b8f91..97ce5a7c77 100644
--- a/src/mainboard/google/herobrine/romstage.c
+++ b/src/mainboard/google/herobrine/romstage.c
@@ -5,6 +5,7 @@
#include <soc/qclib_common.h>
#include "board.h"
#include <soc/shrm.h>
+#include <soc/cpucp.h>
static void prepare_usb(void)
{
@@ -18,6 +19,7 @@ static void prepare_usb(void)
void platform_romstage_main(void)
{
shrm_fw_load_reset();
+ cpucp_prepare();
/* QCLib: DDR init & train */
qclib_load_and_run();
prepare_usb();
diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc
index 85508e97bb..a20d49b8cd 100644
--- a/src/soc/qualcomm/sc7280/Makefile.inc
+++ b/src/soc/qualcomm/sc7280/Makefile.inc
@@ -27,6 +27,7 @@ verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
################################################################################
romstage-y += cbmem.c
romstage-y += shrm_load_reset.c
+romstage-y += cpucp_load_reset.c
romstage-y += ../common/qclib.c
romstage-y += ../common/mmu.c
romstage-y += mmu.c
diff --git a/src/soc/qualcomm/sc7280/cpucp_load_reset.c b/src/soc/qualcomm/sc7280/cpucp_load_reset.c
index cfb16879de..6f8f51ff9f 100644
--- a/src/soc/qualcomm/sc7280/cpucp_load_reset.c
+++ b/src/soc/qualcomm/sc7280/cpucp_load_reset.c
@@ -11,13 +11,11 @@
void cpucp_prepare(void)
{
- /* allow NS access to EPSS memory*/
+ /* allow NS access to EPSS memory */
setbits32(&epss_top->access_override, 0x1);
- /* Enable subsystem clock. Required for CPUCP PDMEM access*/
+ /* Enable subsystem clock. Required for CPUCP PDMEM access */
setbits32(&epss_fast->epss_muc_clk_ctrl, 0x1);
- if (!wait_ms(300, ((read32(&epss_fast->epss_muc_clk_ctrl) & 0x1) != 0x1)))
- printk(BIOS_ERR, "%s: cannot get CPUCP PDMEM access.\n", __func__);
}
void cpucp_fw_load_reset(void)
@@ -25,7 +23,8 @@ void cpucp_fw_load_reset(void)
struct prog cpucp_fw_prog =
PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp");
- cpucp_prepare();
+ if (!wait_ms(300, (read32(&epss_fast->epss_muc_clk_ctrl) & 0x1) == 0x1))
+ printk(BIOS_ERR, "%s: cannot get CPUCP PDMEM access.\n", __func__);
if (!selfload(&cpucp_fw_prog))
die("SOC image: CPUCP load failed");
--
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