From ddcf5a05e3168fbb4565a2a52c14c246822454b2 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 6 Aug 2018 10:40:07 +0200 Subject: mb/asus/kfsn4-dre: Use common pnp_{enter,exit} functions Change-Id: I4b0577bf3c00307733a1096749c1835d86764f29 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/27867 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Paul Menzel --- src/mainboard/asus/kfsn4-dre/romstage.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 2809f0fe91..cc198c6975 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -343,9 +343,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Initialize GPIO */ /* Access SuperIO GPI03 logical device */ - uint16_t port = GPIO3_DEV >> 8; - outb(0x87, port); - outb(0x87, port); + pnp_enter_conf_state(GPIO3_DEV); pnp_set_logical_device(GPIO3_DEV); /* Set GP37 (power LED) to output */ pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); @@ -355,7 +353,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c); pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04); /* Restore default SuperIO access */ - outb(0xaa, port); + pnp_exit_conf_state(GPIO3_DEV); } /** -- cgit v1.2.3