From dd48b176f31fb99218ff805000d7e630f00921de Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 11 Jun 2020 23:31:56 -0600 Subject: mb/google/dedede: Add support for 16 MiB flash map descriptor Upcoming variant boards will use 16 MiB SPI ROM. So add support for 16 MiB flash map descriptor. BUG=b:155107866,b:152981693 TEST=Build different variant boards. Ensure that waddledoo which is using 32 MiB SPI ROM boots. Cq-Depend: chrome-internal:3107306 Change-Id: I8a6868da3280a662ff3a30623804ff135e6cbfbc Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/42322 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/Kconfig | 6 +++ src/mainboard/google/dedede/Kconfig.name | 2 - .../google/dedede/chromeos-dedede-16MiB.fmd | 44 ++++++++++++++++++++ .../google/dedede/chromeos-dedede-32MiB.fmd | 47 ++++++++++++++++++++++ src/mainboard/google/dedede/chromeos.fmd | 47 ---------------------- 5 files changed, 97 insertions(+), 49 deletions(-) create mode 100644 src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd create mode 100644 src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd delete mode 100644 src/mainboard/google/dedede/chromeos.fmd (limited to 'src') diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index a4b2dc1a76..fe3b886d7d 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,5 +1,6 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n + select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI @@ -47,6 +48,11 @@ config DIMM_SPD_SIZE config DRIVER_TPM_SPI_BUS default 0x1 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 + config MAINBOARD_DIR string default "google/dedede" diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 8831d3e0f6..4e2a45068b 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -2,7 +2,6 @@ config BOARD_GOOGLE_BOTEN bool "Boten" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP - select BOARD_ROMSIZE_KB_32768 config BOARD_GOOGLE_DEDEDE bool "Dedede" @@ -35,4 +34,3 @@ config BOARD_GOOGLE_WHEELIE bool "Wheelie" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP - select BOARD_ROMSIZE_KB_32768 diff --git a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd new file mode 100644 index 0000000000..09b2abc208 --- /dev/null +++ b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd @@ -0,0 +1,44 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x381000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x380000 + } + SI_BIOS@0x381000 0xc7f000 { + RW_LEGACY(CBFS)@0x0 0x1000 + RW_SECTION_A@0x1000 0x420000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x40ffc0 + RW_FWID_A@0x41ffc0 0x40 + } + RW_SECTION_B@0x421000 0x420000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x40ffc0 + RW_FWID_B@0x41ffc0 0x40 + } + RW_MISC@0x841000 0x3e000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x3000 + RW_SHARED@0x33000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x37000 0x2000 + RW_NVRAM(PRESERVE)@0x39000 0x5000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x87f000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd new file mode 100644 index 0000000000..60ea3ded64 --- /dev/null +++ b/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd @@ -0,0 +1,47 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0x1b00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0xf00000 + RW_SECTION_A@0xf00000 0x3e0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3cffc0 + RW_FWID_A@0x3dffc0 0x40 + } + RW_SECTION_B@0x12e0000 0x3e0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3cffc0 + RW_FWID_B@0x3dffc0 0x40 + } + RW_MISC@0x16c0000 0x40000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x38000 0x2000 + RW_NVRAM(PRESERVE)@0x3a000 0x6000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1700000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/google/dedede/chromeos.fmd b/src/mainboard/google/dedede/chromeos.fmd deleted file mode 100644 index 60ea3ded64..0000000000 --- a/src/mainboard/google/dedede/chromeos.fmd +++ /dev/null @@ -1,47 +0,0 @@ -FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x500000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x4ff000 - } - SI_BIOS@0x500000 0x1b00000 { - # Place RW_LEGACY at the start of BIOS region such that the rest - # of BIOS regions start at 16MiB boundary. Since this is a 32MiB - # SPI flash only the top 16MiB actually gets memory mapped. - RW_LEGACY(CBFS)@0x0 0xf00000 - RW_SECTION_A@0xf00000 0x3e0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3cffc0 - RW_FWID_A@0x3dffc0 0x40 - } - RW_SECTION_B@0x12e0000 0x3e0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3cffc0 - RW_FWID_B@0x3dffc0 0x40 - } - RW_MISC@0x16c0000 0x40000 { - UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x20000 - } - RW_ELOG(PRESERVE)@0x30000 0x4000 - RW_SHARED@0x34000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD(PRESERVE)@0x38000 0x2000 - RW_NVRAM(PRESERVE)@0x3a000 0x6000 - } - # Make WP_RO region align with SPI vendor - # memory protected range specification. - WP_RO@0x1700000 0x400000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x3000 - COREBOOT(CBFS)@0x4000 0x3f8000 - } - } - } -} -- cgit v1.2.3