From dcce5a33e95b1fa3c09a0ab0a9e951336cbf096e Mon Sep 17 00:00:00 2001 From: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Date: Tue, 8 Aug 2023 12:29:23 -0500 Subject: mb/google/kahlee: enable uart0 for console in devicetree Kahlee selects AMD_SOC_CONSOLE_UART causing UART0 to be used as console, so enable uart_0 in the devicetree to make sure that the UART will be marked as enabled in the SSDT that will be generated with the next patch applied. This also matches the other AMD SoC based Chromebooks. Change-Id: Ibe18f87d8bf63603fb2eb87728395e45e9a9ef69 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77094 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> --- src/mainboard/google/kahlee/variants/baseboard/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb index 632ffa3e9a..92c0d14803 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb @@ -109,4 +109,7 @@ chip soc/amd/stoneyridge device i2c 10 on end end end + + device ref uart_0 on end # console + end #chip soc/amd/stoneyridge -- cgit v1.2.3