From dc17d2de346008aa648aab626dd2a8593b082685 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Mon, 1 Feb 2016 11:21:47 +0530 Subject: soc/qualcomm/ipq40xx: Update the list of MBNs needed for this SoC BUG=chrome-os-partner:49249 chrome-os-partner:50928 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: a48131897217a6e48927d5aafc855a86551c35ca Original-Change-Id: Ia7bab63e5abfb99ab0c03e0e2879149597b7355f Original-Signed-off-by: Varadarajan Narayanan Original-Reviewed-on: https://chromium-review.googlesource.com/333294 Original-Commit-Ready: David Hendricks Original-Tested-by: David Hendricks Original-Reviewed-by: David Hendricks squashed: soc/qualcomm/ipq40xx: Add Kconfig option for SBL binary path BUG=chrome-os-partner:49249 TEST=Compiles... BRANCH=none Original-Commit-Id: 8f0899e3c69737ec7ba579979dae342673bf3962 Original-Change-Id: If199f755106dc58b55ee0499e05304f0ea117bee Original-Signed-off-by: Varadarajan Narayanan Original-Reviewed-on: https://chromium-review.googlesource.com/333307 Original-Commit-Ready: David Hendricks Original-Tested-by: David Hendricks Original-Reviewed-by: David Hendricks soc/qualcomm/ipq40xx: Add rules to combine vendor binary and CB binaries BUG=chrome-os-partner:49249 TEST=Compiles... BRANCH=none Original-Commit-Id: d4b49d37c5b6f86a3bc360051904175111e1db2b Original-Change-Id: I85fde202213b47d5e7c9af3a8d920da20cf456fa Original-Signed-off-by: Varadarajan Narayanan Original-Reviewed-on: https://chromium-review.googlesource.com/333308 Original-Commit-Ready: David Hendricks Original-Tested-by: David Hendricks Original-Reviewed-by: David Hendricks Change-Id: I91b873894975f0a88babc2e2ecdbe5676ee17c0b Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/14649 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/qualcomm/ipq40xx/Kconfig | 19 +++++++++++++++---- src/soc/qualcomm/ipq40xx/Makefile.inc | 18 +++++------------- 2 files changed, 20 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index a122ac9eb2..86db09b8e5 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -22,13 +22,24 @@ config MBN_ENCAPSULATION bool "bootblock encapsulation for ipq40xx" default y -config SBL_BLOB +config CDT_MBN + string "CDT binary blob" + default "cdt-AP.DK01.1-C1.bin" + +config DDR_MBN + string "DDR driver binary blob" + default "ddr.mbn" + +config TZ_MBN + string "TZ binary blob" + default "tzbsp_no_xpu.mbn" + +config SBL_ELF depends on USE_BLOBS - string "file name of the Qualcomm SBL blob" - default "3rdparty/blobs/cpu/qualcomm/ipq40xx/uber-sbl.mbn" + string "file name of the QCA SBL ELF" + default "3rdparty/blobs/cpu/qualcomm/ipq40xx/sbl.elf" help The path and filename of the binary blob containing ipq40xx early initialization code, as supplied by the vendor. - endif diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index 95a78b3ce9..a8d9b1bcc2 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -52,25 +52,17 @@ ramstage-y += tz_wrapper.S ifeq ($(CONFIG_USE_BLOBS),y) -# Add MBN header to allow SBL3 to start coreboot bootblock -$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin - @printf " ADD MBN $(subst $(obj)/,,$(@))\n" - ./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp - @mv $@.tmp $@ - -# Create a complete bootblock which will start up the system -$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \ - $(objcbfs)/bootblock.mbn - @printf " MBNCAT $(subst $(obj)/,,$(@))\n" - @util/ipqheader/mbncat.py -o $@.tmp $^ - @mv $@.tmp $@ +$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_ELF)) \ + $(objcbfs)/bootblock.elf + @printf " CRXBL $(subst $(obj)/,,$(^)) $(subst $(obj)/,,$(@))\n" + @util/ipqheader/createxbl.py -f $(CONFIG_SBL_ELF) -s $(objcbfs)/bootblock.elf -o $@ -a 32 -b 32 endif CPPFLAGS_common += -Isrc/soc/qualcomm/ipq40xx/include # List of binary blobs coreboot needs in CBFS to be able to boot up this SOC -mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn +mbn-files := $(CONFIG_CDT_MBN) $(CONFIG_DDR_MBN) $(CONFIG_TZ_MBN) # Location of the binary blobs mbn-root := 3rdparty/blobs/cpu/qualcomm/ipq40xx -- cgit v1.2.3