From dbfbfaf608c330515c1702bd4eba3b59727bc4df Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 28 Feb 2023 07:01:26 +0000 Subject: drivers/intel/fsp2_0: Have provision for caching TOM region This patch enables early caching of TOM region to optimize the boot time if valid mrc cache is found (i.e. except the first boot after flashing/updating few AP firmware image). TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Subrata Banik Change-Id: Ia575ad0f99d5b0fd015e40b0862e8560700f6c83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73334 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal --- src/drivers/intel/fsp2_0/memory_init.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src') diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index dcb44f6a18..4f0dbf6148 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -24,6 +24,10 @@ #include #include +#if CONFIG(SOC_INTEL_COMMON_BASECODE_TOM) +#include +#endif + static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) @@ -255,6 +259,12 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) die_with_post_code(POST_INVALID_VENDOR_BINARY, "FSPM_ARCH_UPD not found!\n"); + /* Early caching of TOM region if valid mrc cache data is found */ +#if (CONFIG(SOC_INTEL_COMMON_BASECODE_TOM)) + if (arch_upd->NvsBufferPtr) + early_tom_enable_cache_range(); +#endif + /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version); -- cgit v1.2.3