From daf834a705e167efc56e72dfb244d161a9605a9d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Wed, 23 Nov 2022 14:41:29 +0100
Subject: soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-S
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According to ADL PCH BIOS specification (DOC# 630603) ADL-S PCH
uses a fixed SBREG_BAR of 256MiB starting at 0xe0000000.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ied59a6dad8fb065dc3aeb6281bd32074aaa5e3b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
---
 src/soc/intel/alderlake/include/soc/iomap.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src')

diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h
index 6dd3bec140..b451a727d1 100644
--- a/src/soc/intel/alderlake/include/soc/iomap.h
+++ b/src/soc/intel/alderlake/include/soc/iomap.h
@@ -123,6 +123,10 @@
 #define TCO_BASE_SIZE		0x20
 
 #define P2SB_BAR		CONFIG_PCR_BASE_ADDRESS
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#define P2SB_SIZE		(256 * MiB)
+#else
 #define P2SB_SIZE		(16 * MiB)
+#endif
 
 #endif
-- 
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