From d866e5872d5570fded81a4d392884725009a17dd Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Wed, 11 Jun 2014 09:35:37 -0600 Subject: fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOT While pushing the fsp_baytrail code, it was requested that we change CONFIG_ENABLE_FAST_BOOT to CONFIG_ENABLE_FSP_FAST_BOOT. These were missed in the change. Change-Id: If8af3f90b0f5cc9154ff1d3a387f442430f42dee Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/5972 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith Reviewed-by: Paul Menzel --- src/mainboard/intel/bayleybay_fsp/Kconfig | 2 +- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index eaf4f22d8f..8dcc199bde 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -68,7 +68,7 @@ config FSP_FILE config MRC_CACHE_LOC_OVERRIDE hex default 0xfff80000 - depends on ENABLE_FAST_BOOT + depends on ENABLE_FSP_FAST_BOOT config CBFS_SIZE hex diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 87fe5aec50..60a1f7af7e 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -314,7 +314,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, pFspInitParams->NvsBufferPtr = NULL; pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; -#if IS_ENABLED(CONFIG_ENABLE_FAST_BOOT) +#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT) /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif -- cgit v1.2.3