From d84ace50e35d60fe29e6718c33dd7e1e5ea937bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 5 Jan 2023 18:05:11 +0200 Subject: mb/google: Re-arrange mainboard_smi_sleep() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change the order of enabling EC and GPE wake sources, so it comes more obvious we can use existing chromeec handlers without changes. Change-Id: I5a10afa2b816dc8c01074be68a63114ee027c1e2 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/74604 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/google/cyan/smihandler.c | 15 ++++++++++----- src/mainboard/google/rambi/smihandler.c | 9 +++++++-- src/mainboard/intel/strago/smihandler.c | 9 +++++++-- 3 files changed, 24 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index efd6efe5d0..4dd2e0e804 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -37,15 +37,10 @@ void mainboard_smi_sleep(uint8_t slp_typ) switch (slp_typ) { case ACPI_S3: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; case ACPI_S5: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - /* Disabling wake from SUS_GPIO1 (TOUCH INT) and * SUS_GPIO7 (TRACKPAD INT) in North bank as they are not * valid S5 wake sources @@ -54,7 +49,17 @@ void mainboard_smi_sleep(uint8_t slp_typ) GPIO_WAKE_MASK_REG0); mask = ~(GPIO_SUS1_WAKE_MASK | GPIO_SUS7_WAKE_MASK); write32(addr, read32(addr) & mask); + break; + } + switch (slp_typ) { + case ACPI_S3: + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + break; + case ACPI_S5: + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); break; } diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index 5d3329fbf5..3c0743a4f4 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -28,11 +28,16 @@ void mainboard_smi_sleep(uint8_t slp_typ) switch (slp_typ) { case ACPI_S3: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; + } + + switch (slp_typ) { + case ACPI_S3: + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + break; case ACPI_S5: /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index 6d29df8437..40a85448a8 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -33,11 +33,16 @@ void mainboard_smi_sleep(uint8_t slp_typ) switch (slp_typ) { case ACPI_S3: - /* Enable wake events */ - google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; + } + + switch (slp_typ) { + case ACPI_S3: + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + break; case ACPI_S5: /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); -- cgit v1.2.3