From d6da4ef69e4ec8decbaee41297c3a96686021567 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 7 Oct 2021 00:39:31 +0530 Subject: soc/intel/alderlake: Skip setting D0I3 bit for HECI devices This patch skips setting D0I3 bit for all HECI devices by FSP. BUG=b:200644229 TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is set to `1`. Change-Id: I86d61c49b8f187611efd495712ad901184665f31 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/57815 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/fsp_params.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 4ae25371cb..333957f2ea 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -599,6 +599,8 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { + /* Skip setting D0I3 bit for all HECI devices */ + s_cfg->DisableD0I3SettingForHeci = 1; /* * Power Optimizer for DMI * DmiPwrOptimizeDisable is default to 0. -- cgit v1.2.3