From d635068ffaf97d5d94f3e2b2ccee409ed44b0b41 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 18 May 2012 12:47:02 +0200 Subject: smsc/lpc47n227: Make early_serial usable This is the smallest possible change to make early_serial.c compile when included from romstage.c. early_serial could be reworked to be built as separate unit (romstage-y), but that should be done for all SuperIOs, not some individual outlier. Change-Id: I90ee66b43c9677b86b1b5d6fcc8febfbe58d80dd Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/1686 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/superio/smsc/lpc47n227/early_serial.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c index 32bd3e3680..a60dc48a95 100644 --- a/src/superio/smsc/lpc47n227/early_serial.c +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -41,10 +41,13 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) { /* LPC47N227 requires base ports to be a multiple of 4. */ + /* it's not very useful to do an ASSERT here: if it trips, + * there's no console to report it. ASSERT(!(iobase & 0x3)); + */ switch (dev & 0xFF) { case LPC47N227_PP: @@ -73,7 +76,7 @@ void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param enable 0 to disable, anythig else to enable. */ -void lpc47n227_pnp_set_enable(device_t dev, int enable) +static void lpc47n227_pnp_set_enable(device_t dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; -- cgit v1.2.3