From d5b7c55c46ed342dd0817f17138e4655c06b0303 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Thu, 31 Mar 2016 13:23:52 -0700 Subject: intel/amenia: Do not manually open up IO windows Do not use devicetree.cb to manually control hardware registers. This interface will be removed in a subsequent commit and replaced with runtime allocation that also does sanity checking. Change-Id: I55561085ea467f19f52110b1a59f45fe290c7f09 Signed-off-by: Alexandru Gagniuc Reviewed-on: https://review.coreboot.org/14582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/intel/amenia/devicetree.cb | 9 --------- 1 file changed, 9 deletions(-) (limited to 'src') diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 46dae8e618..c54e838826 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -7,15 +7,6 @@ chip soc/intel/apollolake register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "0" # SSD - # EC host command range is in 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - register "gen3_dec" = "0x0" - register "gen4_dec" = "0x0" - - # EC also needs 0x200,0x204, 0x60/0x64, 0x62/0x66 - register "lpc_dec" = "0xd00" - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF -- cgit v1.2.3