From d3108d6c898e7789dc7e5c193158476bca7c4a6e Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Wed, 21 Oct 2020 11:16:08 +0800 Subject: mb/google/volteer/var/voxel: Disable SRCCLKREQ1# According to the schematic,SRCCLKREQ1# is not connected,so disable it on voxel. BUG=b:171279034 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: Pan Sheng-Liang Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46612 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/voxel/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index d7a265b010..e8be8e3eb3 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -14,6 +14,9 @@ chip soc/intel/tigerlake .tdp_pl4 = 105, }" + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + device domain 0 on device ref dptf on chip drivers/intel/dptf -- cgit v1.2.3