From d277960eb8f7c8ed068f1823049c701e00ea8e46 Mon Sep 17 00:00:00 2001 From: wxjstz Date: Tue, 6 Jun 2017 16:50:46 +0800 Subject: riscv: Update register address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I triggered a bug, when I try to debug riscv code by spike. This bug is caused by an instruction exception[csrwi 0x320,7]. This is operate for mcounteren. This address is error. 0x306 is right. scounteren is not need to be set, because S-mode code controls it. Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a Signed-off-by: wxjstz Reviewed-on: https://review.coreboot.org/20043 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer --- src/arch/riscv/virtual_memory.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 2c440d24aa..1fff1d170a 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -311,11 +311,10 @@ void mstatus_init(void) set_csr(medeleg, delegate); // Enable all user/supervisor-mode counters using - // v1.9.1 register addresses. + // v1.10 register addresses. // They moved from the earlier spec. // Until we trust our toolchain use the hardcoded constants. // These were in flux and people who get the older toolchain // will have difficult-to-debug failures. - write_csr(/*mucounteren*/0x320, 7); - write_csr(/*mscounteren*/0x321, 7); + write_csr(/*mcounteren*/0x306, 7); } -- cgit v1.2.3