From d149f1db69c9ddde793889931ce8fef931d13cd8 Mon Sep 17 00:00:00 2001
From: Felix Held <felix.held@amd.corp-partner.google.com>
Date: Sat, 4 Apr 2020 02:48:03 +0200
Subject: soc/amd/picasso: Enable cache in bootblock

Unlike prior AMD devices, picasso cannot rely on the cache-as-RAM
setup code to properly enable MTRRs.  Add that capability to the
bootblock_c_entry() function.  In addition, enable an MTRR to cache
(WP) the flash boot device and another for WB of the non-XIP bootblock
running in DRAM.

BUG=b:147042464
TEST=Boot trembyle to payload and make sure bootblock isn't abnormally
slow.

Change-Id: I5615ff60ca196e622a939b46276a4a0940076ebe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38691
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/picasso/bootblock/bootblock.c | 33 +++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

(limited to 'src')

diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c
index 8ae4db3178..6a0fd85078 100644
--- a/src/soc/amd/picasso/bootblock/bootblock.c
+++ b/src/soc/amd/picasso/bootblock/bootblock.c
@@ -2,14 +2,47 @@
 /* This file is part of the coreboot project. */
 
 #include <stdint.h>
+#include <symbols.h>
 #include <bootblock_common.h>
 #include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
 #include <soc/southbridge.h>
 #include <soc/i2c.h>
 #include <amdblocks/amd_pci_mmconf.h>
 
+static void set_caching(void)
+{
+	msr_t deftype = {0, 0};
+	int mtrr;
+
+	/* Disable fixed and variable MTRRs while we setup */
+	wrmsr(MTRR_DEF_TYPE_MSR, deftype);
+
+	clear_all_var_mtrr();
+
+	mtrr = get_free_var_mtrr();
+	if (mtrr >= 0)
+		set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
+	mtrr = get_free_var_mtrr();
+	if (mtrr >= 0)
+		set_var_mtrr(mtrr, (unsigned int)_bootblock, REGION_SIZE(bootblock),
+			     MTRR_TYPE_WRBACK);
+
+	/* Enable variable MTRRs. Fixed MTRRs are left disabled since they are not used. */
+	deftype.lo |= MTRR_DEF_TYPE_EN | MTRR_TYPE_UNCACHEABLE;
+	wrmsr(MTRR_DEF_TYPE_MSR, deftype);
+
+	enable_cache();
+}
+
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
+	set_caching();
 	enable_pci_mmconf();
 
 	bootblock_main_with_basetime(base_timestamp);
-- 
cgit v1.2.3