From d1243fcaad224c90136796b1080712930bcb06f1 Mon Sep 17 00:00:00 2001 From: Jian Tong Date: Mon, 2 Sep 2024 14:26:00 +0800 Subject: mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support Power consumption according to RTS5227 datasheet section 6.4, L0s is not supported, so set it to ASPM_L1. lspci -vvvv -s 01:00 to verify LnkCtl: ASPM L1 Enabled. BUG=b:359409425 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: I87bb0d195566d273951dee6eeb54c9b388dd7607 Signed-off-by: Jian Tong Reviewed-on: https://review.coreboot.org/c/coreboot/+/84177 Reviewed-by: Kun Liu Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/brox/variants/lotso/overridetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index 0f87889b90..09e881593f 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -357,6 +357,7 @@ chip soc/intel/alderlake .clk_src = 3, .clk_req = 3, .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L1, }" chip soc/intel/common/block/pcie/rtd3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" -- cgit v1.2.3