From d0b7a534ce798eff46a2de4857f48e65100c1572 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 29 Oct 2020 11:04:57 +0100 Subject: mb/google/jecht: Use Haswell CPU code Change-Id: I6c106b152bb2824e000232d23c2991898b2c4475 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46946 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/google/jecht/Kconfig | 1 + src/mainboard/google/jecht/devicetree.cb | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index b04cc465fb..1ffc456ba7 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -1,5 +1,6 @@ config BOARD_GOOGLE_BASEBOARD_JECHT def_bool n + select CPU_INTEL_HASWELL select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select SUPERIO_ITE_IT8772F diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 94fd8044c1..08b2c957c7 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -10,7 +10,10 @@ chip soc/intel/broadwell register "gpu_dp_b_hotplug" = "0x06" device cpu_cluster 0 on - device lapic 0 on end + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end end device domain 0 on -- cgit v1.2.3