From cb4672885e636206101a3266fd6ae001447d4f5d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 19:55:10 +0200 Subject: sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register Change-Id: Icecda127a7229c1410c73a6fdd0898430f7eceb2 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40809 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82371eb/isa.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src') diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index efbfb22470..ae35d90b2c 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -27,9 +27,7 @@ static void isa_init(struct device *dev) /* * Enable special cycles, needed for soft poweroff. */ - reg32 = pci_read_config16(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SPECIAL; - pci_write_config16(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SPECIAL); /* * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO) -- cgit v1.2.3