From cb304c1d85ff0a289c8a7244bf6e8adac07cd624 Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Wed, 7 Feb 2018 17:17:05 +0800 Subject: mb/google/poopy/variants/nami: Add Pmax setting This patch adds the Pmax setting in device tree. The Pmax is from MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W. BUG=b:72138778 BRANCH=None TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage & ensure the Pmax value is passed to FSP-S. Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9 Signed-off-by: Gaggery Tsai Reviewed-on: https://review.coreboot.org/23640 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh --- src/mainboard/google/poppy/variants/nami/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index c4819663cc..b830912562 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -229,6 +229,7 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "tcc_offset" = "10" # TCC of 90C + register "psys_pmax" = "101" # Lock Down register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" -- cgit v1.2.3