From c8dfd6d935505ae45783cb1e15ea0a6683938b0c Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Tue, 12 Dec 2023 18:46:52 +0100
Subject: soc/amd/genoa/acpi/soc: add root bridges to DSDT

Add the 4 root bridge devices using the ROOT_BRIDGE macro.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If405a90981e5c1fea51935c520800a245473317e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79467
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/genoa/acpi/soc.asl | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src')

diff --git a/src/soc/amd/genoa/acpi/soc.asl b/src/soc/amd/genoa/acpi/soc.asl
index 00eb48a43a..0959ecab9d 100644
--- a/src/soc/amd/genoa/acpi/soc.asl
+++ b/src/soc/amd/genoa/acpi/soc.asl
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <soc/amd/common/acpi/pci_root.asl>
 #include "globalnvs.asl"
 
 Scope(\_SB) {
@@ -7,4 +8,9 @@ Scope(\_SB) {
 	#include "pci_int_defs.asl"
 
 	#include "mmio.asl"
+
+	ROOT_BRIDGE(S0B0)
+	ROOT_BRIDGE(S0B1)
+	ROOT_BRIDGE(S0B2)
+	ROOT_BRIDGE(S0B3)
 } /* End \_SB scope */
-- 
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